1. Lab 5 JFET Circuits II
February 20, 2015
by Andy Chu
1

2. Introduction
After familiarizing ourselves with nonlinear components with transfer and ouput
characteristics and how dierent currents and resistors eect JFETs in Circuits I,
we are now able to study more unique applications of JFETs. We look at voltage
ampliers, dierential ampliers, JFET linearization, and parisitic oscillations.
When there are high frequencies in circuits, certain components will not behave
like we expect them to be and in this lab we learn how to troubleshoot and
prevent parasitic oscillations in our laboratory. Ampliers are important to
learn about because signal in the brain are small and if we want to analyze
them, they may be crowded by noise so learning how to use ampliers will help
us read these signals. There is a lot of analysis in this lab because when we
increase gain, we cannot point to simply one component because so many of the
components in our circuit eect gain and we must consider them all. Ultimately
this lab is to explore how to increase gain, but at the same time we will develop
a better understanding of which components may actually decrease gain even
though we are chainging its paramaters to increase gain.
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3. Part I
Ampliers
0.1 We constructed the circuit on the right. Before
measuring the voltages in JFET and current, we must ground
the gate by connecting a wire from gate to ground with a wire
so we can allow current to go through feedback. We put min-
igrabbers on gate and source to nd Vgs with a value of -2.515
V and minigrabbers on source and drain to nd Vds with a
value of 10.46V, red minigrabber from point between 47k re-
sistor and drain of JFET and black to ground were hooked up
to nd Vout with value of 12.97V . Ids was measured by using
minigrabbers on source and drain of JFET and we measured
the value of 2.491 mA. We expect gate source voltage to be
negative, since if it were positive we would be forward biasing
and the JFET would burn out! After showing measurements
were as expected and explain. We then applied signal from
Vinto Vout with a 10kHz, 1V p-p sine wave and looked at its
output on the scope by connecting a red minigrabber to Vout
and a black mini grabber to ground. The amp's gain was:
V out
V in
= 3.88V
.992V
= 3.83gainexperimental Our theoretical amps gain
is V out
V in
= RD
Rs+rs
is approximately (RD)
(RS)
gaintheoretical = 4.7kΩ
1kΩ
=
4.7. The GSI said our theoretical and experimental values
were close enough to consider the experimental and predicted
to be agree. Our theoretical is overestimated and is likely due
to considering rs as negligible. The maximum undistorted
output amplitude is (found by varying input voltage): 23.8 V.
We
3

4. can see the distortion: The maximum
voltage is 23.8 V since our power supply is 24V and we cannot
exceed our voltage supplied to circuit. The amplitude mini-
mum happens because to get minimum voltage, we increase
voltage drop across 4.7kΩ, which causes Vs to increase and
causes Vgs to decrease. When Vgs is lowered enough (Vgs con-
tinously gets lowered since we have feedback and the input is
a smaller Vs), we cannot have any more current as seen from
output characteristic curve. We cooled the JFET with circuit
cooler and saw that nothing changed. This happens because
rs changed and since it is so small, it will not have a major im-
pact to our overall gain. We obtained four other JFETS and
we measured and recorded the gain for each JFET to be the
same. We were pretty lucky to get similar enough JFETs: all
with gain of Vout
V in
= 3.8V
.992V
= 3.8V . Our gain output display on
the scope was:. This is most likely be-
cause we had similar JFETS. The gsi said we were pretty good
at picking JFETs and another group also had four matching
JFETs, so it is denitely possible for four JFETs to be close
enough for the gain to be the same.
0.2 We built the circuit below. The Vout oscillates between 60
mV and 100 mV we average this to about 80 mV. The gain
of this circuit is .08V
1V
= .08 . We checked VDS and found
that it was: 0.023V (practically 0). Equation 1 shows that
in theory the gain should substantially increase if the drain
resistor is changed to 47k. We measured the gain by putting
minigrabbers to Vout and Vin and connecting it to a BNC cable
4

5. to the oscilloscope to measure voltage (or use DMM). The gain is
really small because when we have the 47kΩ resistor, there is a
signicant decrease in current. This causes voltage drop across
47kΩ to decrease and voltage across 1kΩ to be small since less
Ids goes through 1kΩ. Since our Ids is small, Vds is small and
we are in the linear region, but a lot of our assumptions are
made for saturated regions and do not apply ie. using equation
1 will not work for this circuit.
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6. 0.3 We used the same circuit from 0.2 and replaced the 1k resistor
with a 500 ohm resistor. This causes the expected gain to
double to around 9.4 since the formula Rd
Rs
= 4.7kΩ
.500V
= 9.4 = G
Once again we measure the gain the same way we did in 0.2
to get: Vout
Vin
= 4.80V
0.98V
= 4.9 . Our actual gain was smaller than
our predicted gain because we did not take rs into account.
The maximum undistorted output amplitude is: 2.3V , where
input voltage was 500 mV. To be sure we actually had the
undistorted waveform, we used 100 mV. Our We cooled the
JFET with circuit cooler and found that the gain increased
appreciably to 5.11. It makes sense that this time cooling
the JFET, we saw a change in gain because our Rs is now
smaller and in our gain equation: Rd/(Rs + rs) and Rd is
not way bigger than rs so rs is not negligible. Cooling the
JFET causes the gain to increase because rs decreases with
temperature. Now, we calculate rs. We now know that G =
4.9 = Rd/(Rs +rs) therefore rs = 460. This formulaic analysis
shows that our gain should be halved since G = Rd/Rs. We
found in lab 4 that rs is around 100Ω so there must be some
other reason that our gain is driven down and mislead us to
think we have a hudge rs. Comparing our gain results in this
problem to 0.1, we see that the gain here is more because the
Rs is a lot smaller in this problem than the other, making the
eects of rs signicant. We measured and recorded gain for
the other four JFETs .624V
.098V
= 6.36, .552V
.098V
= 5.63, .462V
.098V
= 4.71,
and .48V
.098V
= 4.9. The fractional variation in the gain is larger
for this circuit than for circuit in 0.1 because having a smaller
Rs means that the eects of rs are signicant. There is less
voltage drop in drain and this means Vgs is closer to zero and
the output characteristic shows that more current will ow
through drain and source with Vgs closer to 0. This causes
the voltage drop across Rd to be bigger and the Vout will be
bigger since by Ohm's law V = IR. The following pictures
are respectively our circuit, 500mV undistorted output, 100
mV undistorted output, and our experimental gain.
6

7. 0.4 We used the same circuit as 0.3 and added a 1µF capaci-
tor in parallel with the 1k resistor. We assume rs = 100Ω
To calculate the theoretical gain, we must calculate magni-
tude of impedance of Rs and the capacitor and replace Rs in
the gain equation with this magnitude of impedance. |Z| =√
R2 + X2 . Now we nd impedance of resistor and capac-
itance: we use Z = 1/((1/Rs) + jwC) with w = 2π10kHz,
C = 1µF, and Rs = 1kΩ. Now our variables become: Z =
.2532 − 15.91i, soR = .253andX = −15.91 Evaluating results
in: |Z| = 15.91. If we use Rd
rs
instead of Rd
Rs+rs
, we get gain of
40.54. Our experimental and theoretical values are dierent
because our theoeretical value was too big because of the same
efect in gain reduction that happend in number 3. Our exper-
imental value is 2.92
.1
= 29.2We tested frequency dependence
with 20 kHz. This gave us more gain Vout
Vin
= 2.92
.096
= 30.8The ca-
pacitor increases the gain because it lowers impedance when it
is put in parallel to a resistor. Thus |Z| = Rs so Rd
Rs+rs
. Below
is our 20 kHz output that showed there was frequency depen-
dence. Our results when we increase frequency to 20 kHz is
G = Vout
Vin
= 3.64V
0.098V
= 37.1 This large change is likely due to the
fact that magnitude of impedance is smaller than any source
resistance, so rs (which depends on temperature) is more im-
portant than before. Ultimately, the capacitor increases the
gain because adding something in parallel to a resistor will
always decrease the resultant total impedance. Thus |Z| is
smaller than Rs, so Rd
Rd+rs
should be higher. The following
pictures are respectively: output when frequency is changed
to 20 kHz, and sprayed JFET with cooler
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8. Part II
Dierential Ampliers
0.5 We built the dierential amplier below using our matched
pair of JFETs from lab 5. We left the V− input attached only
to its 100k resistor and drove the V+ input with a 1kHz, 0.1
V p-p sine wave. Minigrabbers were hooked to Vout and con-
nected to the oscilloscope to measure amplitude and phase of
output signal. On a second channel, Vinvout was also con-
nected to the oscilloscope and the signal was. Then we re-
versed the setup and drove our signal into V− and checked
the amplitude and phase at Vout and Vinvout. We drove V+
and V− with identical signals and the common mode gain is:
GC =
Vout+Vinvout
2
V++V−
2
. Our dierential gain is: GD = 2Vout
V+−V−
. Our
data is shown below:
5.5 Data V-(Y) Vinvout(B) V+(G) Vout(P)
Common 0.096V 0.036V 0.096V 0.034V Common mode gain: 0.096V
Drive V+ 0.368V 0.096V 0.345V Out of Phase by 180
Drive V- 0.096V 0.345V 0.364V Out of Phase by 180
Unmatched JFET 0.042V 0.096V 0V
8

9. The following pictures are respectively: outputs for driving V+, V-, V+ and
V- , and unmatched JFET.
Then we went back to out rst setup and replaced one JFET with an un-
matched JFET (the results from this is also in the table): This caused Vout
to collapse to 0 and Vinvout to shrink. This makes sense since both sides of
the dierential amplier have the same load line but each JFET has a dierent
characteristic curve. They both must operate at the same Vgs. This causes
one JFET to have larger current and the other to have smaller: Eventually if
current is low enough for one side of the dierential amplier, we get to the
point on that JFET's characteristic curve where we are have negative enough
Vgs to be past the pinch-o voltage, VP and have all current on that side of
the amplier disappear. This explains why we could not get a signal at Vout.
We obviously were past the pinch-o voltage on the right side of our amplier,
killing o all current and all signals that tried to get through on that side. This
was conrmed when we read the voltage drop across the Rd on the right as
0V. The smaller value of Vinvout also makes sense. Our current on the left is
obviously the larger one, so the voltage drop across the Rd on the left is huge,
leaving little room for Vinvout to oscillate (this is similar to what happened in
#2).
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10. 0.6 We built the ciruit below using the ciruit from 0.5 and replaced
the 10k source resistor with a current source made with a
ressitor and JFET in tandem. Same method was used in 0.5 to
make the same measurements. This circuit is supposed to be a
superior dierential amplier. Therefore, our dierential gain
should be larger and our common mode gain should be even
less than 1. As a result our Vout and Vinvout were both larger
when we drove into either V+ or V-(this made dierential gain
larger). Also, when we used unmatched JFETs we got small
values but Vout did not collapse to 0V this time. This means
that even though the JFETs were unmatched the amplier
did not become as defective as before. For our common mode,
however, Vout and Vinvout collapsed to 0, meaning that our
amplier was so good it killed our common mode completely.
Our circuit, data, and ouput are shown below.
5.6 Data V-(Y) Vinvout V+(G) Vout(P)
Drive V+ 0.688V 0.096V 0.688V
Drive V- 0.96V 0.680V 0.688V
Unmatched JFET 0.4V 0.096V 0.4V
Common 0V 0.096V 0V
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11. Part III
JFET Attenuator
0.7 We built the circuit below. We drove the circuit with 1kHz,
0.1 V p-p triangle wave by hooking up the wave generator to
Vin. We vary the output amplitude with the potentiometer
and the wave form always remained a triangle wave, meaning
that the circuit is linear. Vout was connected the oscilloscope
by minigrabbers and coaxial cable. When potentiometer is
closer to 0, Vgs is closer to 0 and when Vgs becomes closer to
0, current through JFET is now greater and potential through
1k is greater so Vout is much smaller than Vin because there is
no more voltage left. This explains why our output attenuates
our signal and is seen in our results. We set the potentiometer
to produce a signal 3/4 as large and recorded what the poten-
tiometer value, input, and output were and is in the table as
follows:
5.7 Data
Largest Undistorted Output Input Potentiometer 3/4 as large output
0.0744V 0.099V -2.795
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12. 0.8 We built the circuit below by using 0.7 and adding two 100k
resistors in series from drain of JFET to gate of JFET. We
set the potentiometer to 3/4 as large as the input and the
largest input signal that passed relatively undistorted was:
Now we set the potentiomter for greatest attainable attenu-
ation. To calculate the drain source resistance, we use 1
Rds
=
2k[(vgs − Vp) − Vds
2
] → Rds = 1
2k[(Vgs−Vp)−
Vds
2
]
We measured the
Vgs by using minigrabbers: red on gate and black on source
to get a value of 6mV and measured Vds to be 12 mV. We
used the curve tracer to get Vp and our value for pinch o was
-2.878V. We calculated the lowest possible JFET drain-source
resistance corresponding to this setting and it came out to be:
Rds = 1
2k[6mV −(−2.878V )−6mV ]
= .1737
k
. The following pictures
are respectively: circuit we built and largest input signal with
undistorted signal, and curve tracer pinch o value .
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13. Part IV
JFET Modulator
0.9 We built the circuit below. We connected the wave generator
input to Vin and an oscilloscope to Vout to read the output.
The wave generator was set to have a signal with 1V p-p and
about 1Mhz frequency. Then we added a 1 kHz 1V p-p sine
wave from another wave generator by putting a T on T2 and
connecting one coaxial cable to the 1.0 µF and the other to the
oscilloscope. We adjusted the potentiometer until our output
wave t nicely in the input sine wave. Fitting our output
wave in our input means we have successfully modulated our
carrier. Our output is correct because the 1Mhz sine wave is
multiplied to our 1kHz sine wave and that is the wave packet
we see. Adjusting the potentiometer will allow We must set
the potentiometer so that the carrier is modulated by the 1
kHz wave. An image of our Vout is also seen below.
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14. 0.10 We attached a 2-meter long wire to the output of the mod-
ulator in 0.9. We obtained an AM radio, tuned it to a quiet
frequency in the AM band. We adjusted the high frequency
carrier signal until we heard 1 kHz tone coming from radio.
Then we replaced the modulating signal from wave generator
with T1 audio signal from distribution box. We listened to
the radio and realized we have just built a low power AM
transmitter.
0.11 Common mode and dierential gains for a dierential ampli-
er built with current source are respectively: Gc = RD
2R1+Rs+rs
→
RD
2Zout+Rs+rs
Gd
RD
Rs+rs
→ RD
Rs+rs
. We got these two formulas by
replacing R1 with Zout.
Part V
Surprise Circuit
0.12 We built the circuit below. The oscilloscope was connected
by coaxial cable and mini grabbers were attached to coaxial
cable and grabbed onto wire between 4.7 k resistor and jfet.
We see that the output is 1.4 V peak to peak. This circuit has
two ampliers that are self-biased. The output of the JFET
on the right will regulate the output of the JFET on the left.
The large impedance due to the small-valued capacitors will
cause We have two capacitors, so we expect to see output to
oscillate. The top smooth wave is when the 0.001 micro farad
capacitor is charging and the shorter smooth wave is when
the 5 pico farad is charging, since the bigger capacitor will
take longer to charge. We see that when we zoom in, there
are exponential curves that increase and decrease. These
exponential curves make sense because RC circuit analysis
reveals that all of capacitors charges and discharges with
exponential values. The two capacitors are simultaneously
discharging and charging. When the .001 micro farad charges
up, the current through 2.2 mego ohm resistor on the right
drops and the Vgs will become small and allow a lot of current
to go to JFET on the right. This causes the 5 pico farad to
have a less current go through it and while the 5 pico farad is
charging and as a result the 2.2 mega ohm resistor on the left
takes most of the current and leaves the Vgs with less current
and causing the JFET on the left to have a lot of current.
This feed back loop causes the two capacitors to charge and
then discharge and this is what we see on the output.
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15. The following pictures are respecitvely: the ciruit we constructed,
output of circuit, and zoomed in output of circuit increasing,
and decreasing.
Part VI
Phase Splitter
0.13 We designed and built a unity gain phase splitter ( a circuit
that splits an input signal into two signals of equal magnitude
and opposite phase) by ... We maximized the undistorted
output amplitude of circuit by adding resistors in series. This
increases the gain because when we add resistors in series,
we increase the resistane and let less current pass through to
the gate. Small gate voltage means Vgs is small and looking
at output characteristic curve, we will have more current go
through JFET.We have equal amplitude for the two waves
because Ids is the same for both resistors and therefore the
voltage drops will be the same. We have opposite phases,
since the JFET is reverse biased and Vout− = −IDRD and
Vout+ = IDRs The following photos are respectively: output
of our circuit, output of improved circuit with series resistors,
and distorted output.
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16. Part VII
High Gain Amplier
0.14 We built the circuit shown below. We chose to use R1It is
possible to making high gain amplier that is almost tem-
perature and component independent. After nish 0.15, then
complete this circuit. The specic values of resistors and ca-
pacitors we used are: that gave us a feedback controlled gain
of approximately 40. We measured the gain to be: This is
less than predicted by feedback ratio because
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17. 0.15 1) The linearizers: 4.7 k resistor and R1 form a voltage di-
vider that makes Vg half of Vd. The feedback for the bottom
JFET causes the smaller Vg to be fed into the gate and cause
a big current to go through JFET and eect Vout and ul-
timately setting gain. 2) The top JFET, 10k resistor, 1k
resistor, 1.0 µF , 100k resistor, and the 12 V supply are
what act as a current source to increase the gain, since all
these components provide current to the gate. By feedback,
the sum of the currents from those components all eect the
JFET. 3) Open-loop gain can be found when we open the
loop with resistor R1 and 0.1µF and the R1 4) The current
through the JFETs are set by the 1 k resistor and Rs. 5)
0.1 micro farad because the 12V voltage source pumps out
voltage 6) The 1 micro farad is the capacitor that increaes
the stiness of the current source by providing a bypass for
AC signals.
17

18. Conclusion I learned that for ampliers, I must be wary of what source re-
sistance sizes I use because if they are too small, little r s must be considered
and it will eect gain. Also there are other things that decrease gain other than
source resistance, so as a follow up, I could work on my graphical analysis to g-
ure out what may cause this decrease in gain. Dierential ampliers are useful
because they have a gain that is equal to sum of dierential gain and common
gain, however, having unmatched JFETs may give rise to the JFET with a lower
pinch o to die and lose signal if the two JFETs are dierent enough. I really
liked the modulator because it showed that small signals and a modulator can
be adjusted so that the output is a multiple of the two waves. I learned that
If I had more time in the laboratory, I would like to test various circuits on
extremely high frequencies and try to gure out what the behavior of certain
components become on extreme frequencies. I would construct circuits I know
what to expect and then turn the frequency to extreme values and see if the
output changes other than simply create some fuzzy noise.
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