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1. OMKAR REVANKAR
7825 McCallum Blvd, apt 515, Dallas, TX-75252. omi4everarsenal@gmail.com | 469-974-4659 | omkarrevankar |
EDUCATION
The University of Texas at Dallas Aug. 2018 – Aug. 2020
M.S in Electrical Engineering (Digital Systems) GPA- 3.3/4.0
Terna Engineering College (University of Mumbai) Sept 2012 – Aug. 2016
B.E. in Electronics Engineering GPA-7.85/10
TECHNICAL SKILLS
EDA TOOLS: Xilinx ISE Design suite, Aldec Riviera Pro, Modelsim, Cadence Virtuoso, Synopsys VCS, Synopsys SiliconSmart,
PrimeTime, Encounter, Synopsys Tetramax, Hspice, Synopsys Design Vision.
LANGUAGE: Verilog HDL (proficient), System Verilog HVL (proficient), System Verilog Assertions, Perl scripting (intermediate),
Python scripting (intermediate), C and JAVA (basics).
CERTIFICATION: Maven Silicon certified Advanced VLSI Design and Verification.
COURSES: Analog IC design, Advanced Digital Logic, VLSI Design, Wireless Sensor Network, Computer Architecture,
Microprocessor System Network.
WORK EXPERIENCE
DESIGN VERIFCATION INTERN, MAVEN SILICON PVT LTD, BANGALORE, INDIA Jan 2017 – Aug. 2017
ROUTER 1X3- DESIGN AND VERIFICATION Feb 2017– Mar 2017
 Designed, synthesized and verified the source code in UVM) environment. The test cases included different
size payload, FIFO full condition, packet which is never read, corrupt packet, simultaneous read and write operation.
AHP to APB BRIDGE IP CORE VERIFICATION May 2017–June 2017
 Architected the class-based verification environment in UVM. Verified the RTL with single master and single slave
for test cases which included different wrap and increment bursts. Generated functional and code coverage for the RTL
verification sign-off.
AMBA-AXI PROTOCOL VERIFICATION June 2017 – July 2017
 Architected the class-based verification environment in UVM. Verified the AMBA-AXI protocol with single master
and single slave and five different interfaces for respective channels for test cases which included simultaneous
read and write operations with different fixed, increment and wrap bursts.
ETHERNET SUBLAYER DESIGN July 2017–Aug 2017
 Designed the Reconciliation Sublayer (RS), Physical Coding Sublayer (PCS) and Physical Medium Attachment
(PMA) layer of the data link and physical layer of OSI model. IEEE 8b/10b encoding and decoding standard were
used to transmit code-groups between the receiver and transmitter block.
PROJECTS
16-bit ALU with 16X16 SYNCHRONOUS RAM Fall 2018
 Worked using Xilinx ISE, Synopsys, Design Vision, PrimeTime, SiliconSmart, Cadence Encounter and Cadence
Virtuoso.
 Implemented a Behavioral Verilog module of a 16-bit ALU with 16x16 Synchronous RAM by using Xilinx ISE.
Synthesized the module and found number of cells further generating a mapped Verilog Netlist through Design vision.
 Designed a standard cell library of 8 cells, ran DRC, LVS, QRC and performed HSPICE simulation.
 Performed library characterization of all the cells using Silicon Smart. Ran Encounter (Automatic placement and routing
tool from cadence) and found worst case delay from Static Timing Analysis using PrimeTime.
DESIGN OF BRANCH PREDICTION SIMULATOR: (Computer Architecture) Fall-2018
 Implementation of simulator for branch prediction using Bimodal, Local and Tournament benchmarks using X86
architecture and GEM5 simulation. Evaluation is done using SPEC Benchmarks.
 Automated the data analyzing parameters using perl scripting to find out efficiency of branch prediction.
CACHE DESIGN AND OPTIMIZATION OF X86 ARCHITECTURE: (Computer Architecture) Fall-2018
 Fine-tuned the cache hierarchy on X86 architecture for 5 benchmarks using GEM5 simulation and python script
 Cost function is used to identify the optimal cache configuration.
REAL TIME TASK MODELS IN LINUX BASED EMBEDDED SYSTEM ARCHITECTURE: Fall-2018
 Implemented POSIX multithreading with semaphore and mutex synchronization to access shared resources.
 Synthesized the real time task models and found the operation of thread level parallelism.
 Designed 3 periodic, 2 aperiodic threads and a parallel mouse thread which runs infinitely to check for any mouse event
for the triggering of aperiodic thread on X86 host machine.
TWO STAGE AMPLIFIER DESIGN Spring -2019
 Designed a differential-input single-ended output Two stage amplifier using 0.35um CMOS technology. The amplifier is
modelled so as to meet the given specifications and keep the system stable. The amplifier design and simulation were done
using Cadence and Hspice.

2. IOT BASED CARBON MONOXIDE SENSOR NETWORK Spring 2019
 Implementing an IOT based solution, using Python and Amazon Web Service, for detecting carbon monoxide threats in
vehicles using pre-existing sensors in cars like GPS, Camera, Lambda Sensor etc. This system reduces false alarms thrown by
everyday CO detection unit thus increasing its reliability.
ADDITIONAL INFORMATION
Personal Skills: Creative and Logical, Leadership qualities, organizing capabilities, Goal attainment, Quick Learner, Problem
solving ability, Innovative, Strategic Thinking, Co-operative and a Keen observer.
Languages: Proficient- English, Hindi, Marathi.
Eligibility: Authorized to work in the United States without sponsorship till 2023 on F1 visa as a part of OPT/ CPT.