Discover FPGAsim and OPAl-RT Power System technology.

1. www.opal-rt.com
Ould Bachir, Tarek
January 8th, 2015
Challenges of Parallel Simulation of
Power Systems

2. 22
Outline
1 2 3 4
Introduction Challenges
Large
Nerworks
Problematic

3. 33
Outline
1 2 3 4
Introduction Challenges
Large
Nerworks
Problematic

4. 44
Power System Simulation
Introduction
Network Simulation Controller Prototyping
Transients Analysis Fault Scenarios

5. 55
Power System Simulation
ePHASORsim
Real-Time Transient
Stability Simulator
10 ms time step
HYPERsim
Large Scale Power System
Simulation for Utilities & Manufacturers
25 µs to 100 µs time step
eFPGAsim
Power Electronics Simulation on FPGA
1 µs to 100 ns time step
1 s
(1 Hz)
10,000
2,000
1,000
500
100
10
0
10 ms
(100 Hz)
50 µs
(20 KHz)
10 µs
(100 KHz)
1µs
(1 MHz)
100 ns
(10 MHz)
10 ns
(100 MHz)
20,000
Transients Period (frequency)
Number of buses
eMEGAsim
Power System & Power Electronics Simulation
Based on Matlab/Simulink and SimPowerSystems
10 µs to 100 µs time step
Introduction
Phase Domain
Time Domain

6. 66
Introduction
The
Host
Controller
Real-Time Simulator

7. 77
Introduction
15-20 years ago, the revolution was to
build simulators from off-the-shelf PC (PCs
were connected in clusters)
HIL Simulators
OP5607 (Virtex 7)
OP4500 (Kintex 7)
CPU computing power is often insufficient,
hence FPGA are often used to offload part
or total of computing load

8. 88
Outline
1 2 3 4
Introduction Challenges
Large
Nerworks
Problematic

9. 99
Problematic
In HIL simulation, a real hardware (i.e. a physical controller) is connected to the simulator.
The simulation loop must be as fast as possible!
Simulated plantPhysical controller
PWM pulse
Analog V/I
Hall Effect

10. 1010
Problematic
• Advances in semiconductor technology allow very high
switching frequencies (10kHz to 100kHz) to be reached
• Such frequencies have various benefits for the power
system: higher power density, lower THD, etc.
• They are however very challenging for real-time simulators
that must achieve time steps below 1 μs
0 5 10 15 20
-0.5
0
0.5
1
1.5
1 kHz PWM (UA)
Logiclevel
Time (ms)
0 5 10 15 20
-20
0
20
Load currents
Current(A)
Time (ms)
0
-0.5
0
0.5
1
1.5
Logiclevel
0
-20
0
20
Current(A)
0 5 10 15 20
-0.5
0
0.5
1
1.5
1 kHz PWM (UA)
Logiclevel
Time (ms)
0 5 10 15 20
-20
0
20
Load currents
Current(A)
Time (ms)
0 5 10 15 20
-0.5
0
0.5
1
1.5
20 kHz PWM (UA)
Logiclevel
Time (ms)
0 5 10 15 20
-20
0
20
Load currents
Current(A)
Time (ms)

11. 1111
Problematic
• To meet such tight timing requirements, FPGA-based real-
time simulation has proven to be an effective solution
(the only one in fact!)
• However, solving differential algebraic equations (DAEs) on
FPGA means designing an application specific processor
(ASP) from scratch!
Physical controller
PWM pulse
Simulated plant
FPGA

12. 1212
Outline
1 2 3 4
Introduction Challenges
Large
Nerworks
Problematic

13. 1313
Challenges
• Technical challenges:
• Number format: Floating-Point (FP) vs. Fixed-Point (FXP)
• FP Operators have long latencies
• Clock Frequency: how to increase it with minimal impact on the latency
• How to model power converters (switched networks)
• Practical challenges:
• FPGA programming is tedious and requires special skills (end user is a
power electronics specialist)
• Programming and reprogramming times are long: objective is to avoid the
penalty on prototyping

14. 1414
Solutions to technical challenges
• Self-Alignement technique

15. 1515
Solutions to technical challenges
• High Radix Carry Save (HRCS) used to reduce latency of the FP operators

16. 1616
Solutions to technical challenges
• Custom operators with fused-path

17. 1717
Solutions to practical challenges

18. 1818
Solutions to practical challenges
• Architecture of the computing engine
Blocks RAM, CPU
reprogrammable

19. 1919
Solutions to practical challenges
Workflow
Host Computer
(Console)
Design Power
Electronics Circuit
Real-Time
Simulator
Execute the CPU Model
FPGA
Execute the power
converter model on FPGA
No hardware design
skills required
No reprogramming
No bitstream generation
Physical
controller
HIL Simulation

20. 2020
Outline
1 2 3 4
Introduction Challenges
Large
Nerworks
Problematic

21. 2121
Large networks simulation
HVDC Transmission System
MMC 2MMC 1
1GW
± 320 kV
C = 10mF
Larm = 50mH
C = 10mF
Larm = 50mH
Bypass
breaker 1
Rstart = 100Ω
Bypass
breaker 2
Rstart = 100Ω70 km DC cable
1 2 12
Main ac
breaker 1
Main ac
breaker 2
AC EQ.
SRC1
AC EQ.
SRC2
CPU #1:
Eq. Source no 1
CPU #2: VSC-MMC Station no. 1 CPU #3: VSC-MMC Station no. 2
CPU #4:
Eq. Source no 2
Low Level
Control
CPU #6: Inverter Control
Upper Level
Control
Upper Level
Control
CPU #5: Rectifier Control
Low Level
Control
MMC Converters
Simulated on FPGA

22. 2222
Large networks simulation
MMC Structure
400 SM
eq. 9600 semi-conducteurs
MMC Computing Engine
Architecture

23. 2323
0 0.5 1 1.5 2 2.5 3 3.5
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
vua(pu)
time (s)
0 0.5 1 1.5 2 2.5 3 3.5
-4
-3
-2
-1
0
1
2
3
4
5
iua(pu)
time (s)
0 0.5 1 1.5 2 2.5 3 3.5
0
5
10
15
20
25
30
35
VctotupA(pu)
time (s)
CPU MMC
FPGA MMC
Large networks simulation
Perfect match with the offline simulation reference

24. 2424
0 0.5 1 1.5 2 2.5 3 3.5
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
vua(pu)
time (s)
0 0.5 1 1.5 2 2.5 3 3.5
-4
-3
-2
-1
0
1
2
3
4
5
iua(pu)
time (s)
0 0.5 1 1.5 2 2.5 3 3.5
0
5
10
15
20
25
30
35
VctotupA(pu)
time (s)
CPU MMC
FPGA MMC
Large networks simulation
Perfect match with the offline simulation reference

25. 2525
2.44 2.46 2.48 2.5 2.52 2.54 2.56
0
0.2
0.4
0.6
0.8
1
1.2
vua(pu)
time (s)
2.45 2.46 2.47 2.48 2.49 2.5 2.51 2.52 2.53 2.54 2.55
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
iua(pu)
time (s)
2.45 2.46 2.47 2.48 2.49 2.5 2.51 2.52 2.53 2.54 2.55
370
380
390
400
410
420
430
440
450
VctotupA(pu)
time (s)
CPU HVDC
FPGA HVDC
Large networks simulation
Perfect match with the offline simulation reference

26. 2626
Thank you for
your kind attention.
www.opal-rt.com
Acta est fabula
Contact:
Tarek Ould Bachir
R&D Engineer
tarek@opal-rt.com
Opal-RT Technologies