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# 電流臨界モード方式PFC制御回路の解説書

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### 電流臨界モード方式PFC制御回路の解説書

2. 2. Contents• Introduction• Application Circuit• Design Specification• Time Scaling• Application Circuit with Time Scaling (tscale =10)• Common Mode Choke Coil for PFC• Design Steps (1-8)• Switching Devices VPEAK and IPEAK at Steady State• Switching Devices VPEAK and IPEAK at Start UpAppendixA.Excel Calculation SheetB.Simulation IndexAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 2
3. 3. IntroductionMost electronic ballasts and switching power supplies use a bridge rectifierand a bulk storage capacitor to derive raw dc voltage from the utility ac line,figure above: Vin=100Vac, 50Hz and PO=200W.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 3VinAC_IN1PARAMETERS:f req = 50HzVin = 100VacAC_IN2Cbulk2000uF0bulkDB1DB2DB3DiodeDB4Load1.414AdcIlineVbulk
4. 4. Time160ms 164ms 168ms 172ms 176ms 180ms 184ms 188ms 192ms 196ms 200msAVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))00.20.40.60.81.0ABS( I(Vin) )0A10A20AABS( V(AC_IN1,AC_IN2) ) V(bulk)0V100V200VSEL>>IntroductionThe Uncorrected Power Factor rectifying circuit draws current from the ac linewhen the ac voltage exceeds the capacitor voltage (Vbulk). The current (Iline) is non-sinusoidal. This results in a poor power factor condition where the apparent inputpower is much higher than the real power, figure above, power factor ratios of 0.5 to0.7 are common.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 4|VAC, in, 100V| (VPEAK, in=100*2=141.42V) and Vbulk|Iline|Power Factor Ratio = Pin, avg./(Vin, rms* Iin, rms)
5. 5. Vac, inC11uFC2200uILoad0.5AL112DiodeD2Q1MOSFETR7L21 200Rectifiers PFCTB6819AFGControllerCircuitPARAMETERS:f req = 50HzVin = 100VacIntroductionThe Power Factor Correction (PFC) circuit, as an off-line active preconverter, isdesigned to draw a sinusoidal current from the AC line that is in phase with inputvoltage. As a result, the power factor ratio is improved to be near to ideal (1).The TB6819AFG is a critical conduction mode (CRM) PFC controller IC. Thedescription including equation and constants as a guide to understand its designingprocess is included in this document.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 5IlineVDC, OUT
6. 6. Time*10100ms 104ms 108ms 112ms 116ms 120ms 124ms 128ms 132ms 136ms 140msAVG(ABS(W(Vin))) / (RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))00.20.40.60.81.0-I(Vin)-8.0A0A8.0ASEL>>1 V(AC_IN1,AC_IN2) 2 V(VOUT)-160V0V160V1200V400V600V2>>IntroductionThe poor power factor load is corrected by keeping the ac line current sinusoidal and inphase with the line voltage. This results with power factor ratio is 0.85.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 6VAC, in, 100V and VDC, OUT, 400VIlinePower Factor Ratio = 0.85*simulation result at tscale = 10
7. 7. Load0.5AR1239kC90.1uFVinFREQ = {f req}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 100C6 3300pAC_IN2C11u00R93MEGR1022kC510nFC847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC30.47uFIC = 3.74L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC41uFVOUTR21.5MEGR19.53kC2 200uFIC = {2.51*1509.53/9.53}COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Application CircuitAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 7VAC, in=85-265VACPO = 200W,VDC, OUT = 400VDC*Analysis directives:.TRAN 0 20ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
8. 8. Time10ms 11ms 12ms 13ms 14ms 15ms 16ms 17ms 18ms 19ms 20msAVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))00.51.0Time0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms-I(Vin)-10A0A10ASEL>>1 V(AC_IN1,AC_IN2) 2 V(VOUT)-200V0V200V1380V400V420V2>>Application CircuitAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 8VAC, in, 100V and VDC, OUT, 400VIlinePower Factor Ratio = 0.85Total simulation time = 1429.49 seconds
9. 9. Design SpecificationThis application circuit is for 400VDC/200W outputCritical Conduction Mode (CRM) PFC Circuit :• VAC, in,min = 85 (VAC)• VAC, in,max = 265 (VAC)• VO = 400 (VDC)• Po = 200 (W)• fs = 20kHz ~ 150kHz, 50kHz•  (assumed) = 90%Control IC :• Part # TTB6819AFG (PFC Controller IC)• Switching Technique: Critical Conduction Mode (CRM)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 9
10. 10. Time ScalingThe transient (cycle-by-cycle) simulation of PFC circuits is really time (and memory)consuming exercise, even with a fast computer.There is a way to speed up simulations by artificially altering some of the key element valuesby using of time scaling ratio (tscale), passed as a parameter to the simulation engine:• Fline = F line  tscale• C 2 = C 2  tscale• C 3 = C 3  tscale• C 4 = C 4  tscale• C 5 = C 5  tscaleAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 10
11. 11. Application Circuit with Time Scaling (tscale =10)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 11VAC, in=85-265VACPO = 200W,VDC, OUT = 400VDC*Analysis directives:.TRAN 0 2ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100uLoad0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 100C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 3.74L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4PARAMETERS:tscale = 10DB2DB3DiodeDB4Q1MOSFETR510
12. 12. Time*1010ms 11ms 12ms 13ms 14ms 15ms 16ms 17ms 18ms 19ms 20msAVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))00.51.0Time*100s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms-I(Vin)-10A0A10ASEL>>1 V(AC_IN1,AC_IN2) 2 V(VOUT)-200V0V200V1380V400V420V2>>Application Circuit with Time Scaling (tscale =10)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 12VAC, in, 100V and VDC, OUT, 400VIlinePower Factor Ratio = 0.85Total simulation time = 132.41 seconds
13. 13. Common Mode Choke Coil for PFCTo model a simple common mode choke coil, theSPICE primitive k, which describes the coupling ratiobetween L1 and L2, can be used.COUPLING=1 of K_Linear means there is no leakageinductance in the common mode choke coil model.N is a ratio of L2 turns and L1 turns, or N2/N1Input the parameters: L as an L1 inductance valueand N, then L2 is calculated using equation: L2 =N2L1All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 13L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1L2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2
14. 14. Design Steps (1-8)(1) Output Voltage and Feedback Circuit(2) Output Capacitor(3) L1 Inductance(4) Input Capacitor(5) Auxiliary Winding L2(6) Multiplier Input Circuit (MULT)(7) Current Detection Circuit (IS)(8) Zero Current Detection Circuit (ZCD)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 14
15. 15. (1) Output Voltage and Feedback CircuitThe output voltage is resistively divided and applied to the error amplifier, to set the VOthe R1 and R2 resistor value should satisfy the following equation :*With VO=400V and R2=1.5M, R1 is calculated to be 9.47k, however a resistor of 9.53k , whichis available in the E96 series, is used as R1 (actual).All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 152.51RRRV211OOutput DC Voltage, VO 400 VError Amplifier Reference Voltage Verr 2.51 VR2 1.5 MR1 9.47 kR1 (actual) 9.53* k
16. 16. (2) Output CapacitorThe output capacitance C2 is determined so that the PFC output ripple voltage dose notexceed the VOPV-2, for the capacitor selection, the following equation should be satisfied:The value of VOVP-2, min and Verr, min are inform in the TB6819AFG datasheet.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 16PO 200 Wfin 50 HzVO 400 VVOVP-2, min 2.63 VVerr, min 2.46 VC2  41 FC2used 200 F  1-/VVV22PC2err2-OVP2OOinf
17. 17. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 100C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 3.74L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (1) and (2)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 17Vin = 100Vac withfrequency 50Hz,tscale = 10R1=9.53k andR2=1.5MIload = 0.5A asPO=200W atVO=400VC2 =200F*Analysis directives:.TRAN 0 4ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
18. 18. Time*100s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40msV(FB_IN) 2.63 2.462.42.62.8V(VOUT)380V400V420VSEL>>V(AC_IN1,AC_IN2)-200V0V200VSimulation of Step (1) and (2)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 18VAC, in,=100V (VPEAK, in,=100*1.4142=141.4V)V(FB IN), VOVP-2, min.(2.63V), and Verr,min(2.46V)VO=400Vdc with 2fline rippleTotal simulation time = 270.61 seconds
19. 19. (3) L1 InductanceThe switching frequencyfs (Hz) depends on the L1 inductance andinput/output condition which the equation and the calculation data are as shownbelow.*The fs value should be within 20kHz and 150kHz, to avoid an occurrence of EMIproblem, fs=50kHz is used.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 19OO2minin,AC,minin,AC,OPVfs1002V)V2(VL1ηOutput DC Voltage, VO 400 VMinimum AC Input Voltage, VAC, in, min 85 VPower Efficiency,  (assumed) 90 %Switching Frequency, fs* 50 kHzOutput Power, PO 200 WCalculated Inductance, L1(calculated) 227 HSelected (Actual) Inductance, L1(actual) 230 H
20. 20. (4) Input CapacitorC1 should be capable of supplying energy stored in the L1 while the FET is on. Assumedthat the on/off duty is 50%, the C1 should be temporarily able to supply twice the current.A current reaches its maximum at the VAC, in, min. Thus, the following relationship shouldbe satisfied:All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 20L1 230 HPO 200 WVAC, in, min 85 VC1  0.35 FC1used 1 F4minin,AC,2OVPL12C1
21. 21. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 85C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 4.22L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (3) and (4)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 21Vin, min = 85Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400VThe Calculated L1 value227H (adjusted 230His used)I(L1)C1 = 1F*Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
22. 22. Time16.45ms 16.46ms 16.47ms 16.48ms 16.49ms 16.50ms 16.51ms 16.52ms 16.53ms 16.54ms 16.55msV(POUT)0V10V20V-I(L1)0A5A10AV(VOUT)395V400V405VSEL>>Simulation of Step (3) and (4)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 22VO=400Vdc with high switching rippleI(L1)Switching Control Signal, fs = 48.4 kHzTotal simulation time = 976.83 seconds
23. 23. (5) Auxiliary Winding L2The auxiliary winding L2 is used to detect the zero inductor current condition of the inductor L1.Since the maximum reference voltage for the ZCD comparator is 1.9V (the IC specification) ,N1/N2 should meet the following condition:Where N1 is the number of winding of turns of L1, N2 is that of L2*To ensure that the design requirements are met, N1/N2 should preferably about 10 (9.6 isused) to allow for design margins.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 239.1maxin,AC,O V2VN1/N2Output DC Voltage, VO 400 VMaximum AC Input Voltage, VAC, in, max 265 VCalculated Turn Number Ratio, N1/N2 < 14Selected Transformer Turn Ratio, N1/N2 (actual) 9.6*
24. 24. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 265C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 2.533L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (5)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 24N1/N2=9.6, inputparameter N =N2/N1 = 1/9.6I(L1)Vin, min = 265Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400V*Analysis directives:.TRAN 0 4ms 2ms 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
25. 25. Time*1020ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40msV(ZCD) 1.902.55.07.5-I(L1)0A2.5A5.0AV(VOUT)375V400V425VSEL>>V(AC_IN1,AC_IN2)-400V0V400VSimulation of Step (5)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 25VO=400V and PO=200WVAC, in, min=265V (VPEAK, in, min=265*1.4142=374.8V)I(L1)V(ZCD) and the maximum reference voltage of the TB6819AFG’s ZCD comparator, 1.9VTotal simulation time = 1012.86 seconds
26. 26. (6) Multiplier Input Circuit (MULT)The AC input supply voltage (sinewave) is applied to the multiplier by dividing a full-waverectified voltage waveform.The IC startup threshold voltages of the Brown Out Protection (BOP) function = 0.75V andthe MULT linear input voltage range of the multiplier = 0 to 3V, the R9 and R10 resistor shouldsatisfy the following condition:with excel calculation sheet PFC_Cal-Sht.xlsx you can input R9 and R10 values, then check thecalculated BOP and Linear MULT values to be within the maximum values.All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 2610910minin,AC,RRR2V075.Maximum AC Input Voltage, VAC, in, min 400 VMaximum AC Input Voltage, VAC, in, max 265 VR9 3 MR10 22 kMinimum Condition for BOP 0.875 > 0.75Maximum Condition for Linear MULT 2.728 < 3310910maxin,AC,RRR2Vand
27. 27. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 265C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 2.533L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (6) at Vin, maxAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 27Vin, max = 265Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400VR10=3M andR11=22k*Analysis directives:.TRAN 0 4ms 2ms 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
28. 28. Time*1020ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40msV(MULT) 301.02.03.04.0V(Rtf)0V100V200V300V400VV(AC_IN1,AC_IN2)-400V-200V0V200V400VSEL>>Simulation of Step (6) at Vin, maxAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 28Full-wave rectified voltageVAC, in, max=265V (VPEAK, in, min=265*1.4142=374.8V)V(MULT) < MULT linear input maximum voltage (3V)Total simulation time = 1012.86 seconds
29. 29. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 85C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 4.22L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (6) at Vin, minAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 29R10=3M andR11=22kVin, min = 85Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400V*Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
30. 30. Time*10180ms 182ms 184ms 186ms 188ms 190ms 192ms 194ms 196ms 198ms 200msV(MULT) 0.7500.51.0V(Rtf)0V40V80V120VSEL>>V(AC_IN1,AC_IN2)-200V0V200VSimulation of Step (6) at Vin, minAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 30Full-wave rectified voltageVAC, in, min=85V (VPEAK, in, min=85*1.4142=120.2V)V(MULT) > BOP threshold voltage (0.75V)Total simulation time = 976.83 seconds
31. 31. (7) Current Detection Circuit (IS)Iq1 (power switch current) is converted into voltage by R7, then applied to the IS pin. The R7resistor value calculation follows these steps:1) The maximum current of the Q1 current, Iq1 (max) should allow the output power PO to meetthe specification. Therefore, the following equation should be satisfied:2) the IS pin peak voltage (Visp) is calculated using the following equation:3) R7 = Visp / Iq1(max.).All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 31R10R9R102V0.65Visp minin,AC,Minimum ac input voltage, VAC, in, min 85 VOutput power, PO 200 WPower efficiency,  (assumed) 90 %R9 3 MR10 22 kPower switch current, Iq1(max.) 5.23 ATB6819AFG IS pin peak voltage Visp 0.57 VR7 0.11 )2V(η22100PIq1(max.)minin,AC,O
32. 32. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 85C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 4.22L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (7)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 32Iq1R7 =0.11Vin, min = 85Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400VR10=3M andR11=22k*Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
33. 33. Simulation of Step (7)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 33Time*10180ms 182ms 184ms 186ms 188ms 190ms 192ms 194ms 196ms 198ms 200msV(IS)0V0.5V1.0VID(Q1)0A2.0A4.0A6.0A8.0ASEL>>V(MULT)0V0.5V1.0VIq1V(MULT)V(IS)Total simulation time = 976.83 seconds
34. 34. (8) Zero Current Detection Circuit (ZCD)The auxiliary winding L2 is connected to the ZCD pin. The current through L2 is limited to ZCDpin rated current (3mA) by using the current limiting resistor R6. The following relationshipshould be satisfied depending on whether the external FET is on or off:FET = On:FET = Off:A resistor of 68k is used for limiting the current to 1/5 of the rated currentAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 34VAC, in, max 265 VN2/N1 1/9.6 WVO 400 VFET = ON, R6 > 13.0 kFET = OFF, R6 > 13.9 kR6 (actual) 68 k 3mAN2/N12VR6 max.in,AC,  3mAN2/N1VR6 O 
35. 35. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 265C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 2.533L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Simulation of Step (8)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 35ON/OFFR6 =68kVin, max = 265Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400VR10=3M andR11=22k*Analysis directives:.TRAN 0 4ms 2ms 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
36. 36. Time*1020ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40msI(R6) 3m/5-1.0m01.0mV(VOUT)375V400V425VV(AC_IN1,AC_IN2)-400V0V400VSEL>>Simulation of Step (8)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 36VAC, in, max=265VV(VOUT)I(R6) and 1/5 of the ZCD rated current (3mA/5)Total simulation time = 1012.86 seconds
37. 37. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 85C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 4.22L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}IC = {2.51*1509.53/9.53}PARAMETERS:tscale = 10COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Switching Devices VPEAK and IPEAK at Steady StateAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 37Vin, min = 85Vac withfrequency 50Hz,tscale = 10Iload = 0.5A asPO=200W atVO=400VI(D2)SwitchingDiode, D2*Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100uID(Q1)SwitchingMOSFET, Q1
38. 38. Time18.00ms 18.25ms 18.50ms 18.75ms 19.00ms 19.25ms 19.50ms 19.75ms 20.00msID(Q1)-6A0A6A12AV(Q1:d,Q1:s)0V200V400V600VI(D2)8A16A-2ASEL>>V(D2:2,D2:1)0V200V400V600VSwitching Devices VPEAK and IPEAK at Steady StateAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 38D2 VKA, Peak ≈ 400V at steady stateTotal simulation time = 976.83 secondsD2 IF, Peak ≈ 12A at steady stateQ1 VDS, Peak ≈ 400V at steady stateQ1 ID, Peak ≈ 7.2A at steady state
39. 39. Load0.5AR1239kC90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 85C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCC FB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kC2 {200u/tscale}PARAMETERS:tscale = 40COMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2DB1DiodeD2DiodeD3DiodeD4DB2DB3DiodeDB4Q1MOSFETR510Switching Devices VPEAK and IPEAK at Start UpAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 39Vin, min = 85Vac withfrequency 50Hz,tscale = 40Iload = 0.5A asPO=200W atVO=400VI(D2)SwitchingDiode, D2*Analysis directives:.TRAN 0 10ms 0m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100uID(Q1)SwitchingMOSFET, Q1RectifierDiode, DB1-4
40. 40. Time*400s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms 360ms 400ms1 V(Q1:d,Q1:s) 2 ID(Q1)-500V0V500V1-10A0A10A2>>1 V(D2:2,D2:1) 2 I(D2)0V200V400V600V1SEL>>0A6A12A18A2SEL>>1 V(DB1:2,DB1:1) 2 I(DB1)100V200V-10V1>>0A8A16A2V(VOUT)0V200V400V600VSwitching Devices VPEAK and IPEAK at Start UpAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 40V(VOUT) at start upTotal simulation time = 733.5 secondsD2 VKA, Peak ≈ 400V and IF, Peak ≈ 16A at start upQ1 VDS, Peak ≈ 400V and ID, Peak ≈ 10A at start upDB1-4 IF, Peak ≈ 10A at start up
41. 41. Load0.5AR1239kQ22SK2611C90.1uFVinFREQ = {f req*tscale}VAMPL = {Vin*1.414}AC_IN1R4 100PARAMETERS:f req = 50Vin = 100C6 3300pAC_IN2C11u00R93MEGR1022kC5{10n/tscale}C847uFIC = 17.9D5DZ18VR11360kR668kR8100kMULTRtfC3{0.47u/tscale}IC = 3.74L1{L}12PARAMETERS:L = 230uN = {1/9.6}N=N2/N1, L2=(N^2)*L1VCCV1R70.11POUTV2U1TB6819AFGFB_INCOMPMULTISZCDGNDPOUTVCCFB_INISZCDC78pR310kC4{1u/tscale}VOUTR21.5MEGR19.53kCOMPL2{N*N*L}1 2KK1COUPLING = 1K_LinearL1 = L1L2 = L2C2RJJ-35V221MG5-T20D2SCS110AGDB1DiodeD3DiodeD4PARAMETERS:tscale = 10DB2DB3DiodeDB4R510Simulation with Models from the SpicePark (1/4)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 41CapacitormodelMOSFETprofessionalmodelSchottky diodemodelReplace some default model with models from SpicePark*Analysis directives:.TRAN 0 2ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 100.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u
42. 42. Time484us 488us 492us 496us 500us 504us 508us 512us 516us 520us 524usV(V2)0V40V-I(L1)0A5A10AV(V1)0V250V500VV(Q2:g)10V20VSEL>>Time0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0msV(VOUT)392V400VSimulation with Models from the SpicePark (2/4)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 42V(VOUT) with high frequency ripple which is caused by ESR and ESL of the capacitor model.Gate charge characteristics is include in the MOSFET Professional model.V(V1)I (L1)V(V2)Total simulation time = 408.13 seconds
43. 43. Time476us 480us 484us 488us 492us 496us 500us 504us 508us 512us 516usV(V2)0V40V-I(L1)0A5A10AV(V1)0V250V500VV(Q1:g)10V20VSEL>>Time0s 0.5ms 1.0ms 1.5ms 2.0msV(VOUT)392V400VSimulation with Models from the SpicePark (3/4)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 43The Simulation Waveform with the defaults modelsV(V1)I (L1)V(V2)V(VOUT) without high frequency ripple which is caused by ESR and ESL of the capacitor model.Gate charge characteristics is not include in the default model.Total simulation time = 132.41 seconds
44. 44. Simulation with Models from the SpicePark (1/4)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 44SpicePark of MOSFET modelSelect the device which iscapable of handling thesimulated peak values.
45. 45. Excel Calculation Sheet (1/2)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 45Design SpecificationVAC, in,min 85 VVAC, in,max 265 Vfin 50 HzVO 400 VPO 200 Wfs 50 kHz (assumed) 90 %(1) Output Voltage & Feedback CircuitR2 1.5 M ; Input R2 value, the R1 for the VO specification isauto-calculatedR1 9.47 kR1 (actual) 9.53 k(2) Output CapacitorVOVP-2, MIN. 2.63 V ; VOVP-2, MIN. and Verr, MIN. are TB6819AFG electricalcharacteristicsVerr, MIN. 2.46 VC2 ³ 41 uF(3) L1 InductanceL1 227 mHL1(actual) 230 mH
46. 46. Excel Calculation Sheet (2/2)All Rights Reserved Copyright (C) Bee Technologies Corporation 2012 46(4) Input CapacitorC1 ³ 0.35 FC1(actual) 1 F(5) Auxiliary Winding L2N1/N2 < 14N1/N2(actual) 9.6(6) Multiplier Input Circuit (MULT)R9 3 M ; Input R9 and R10 values, then check the BOP andthe Linear MULT valuesR10 22 kCodition:BOP 0.875 > 0.75Linear MULT 2.728 < 3(7) Current Detection Circuit (IS)Iq1(max.) 5.23 AVisp 0.57 VR7 0.11 (8) Zero Current Detection Circuit (ZCD)FET=ON, R8 > 13.0 kFET=OFF, R8 > 13.9 kR8 (actual) 68 k ; limiting the current to 1/5 of the rated current.RemarkInput your design specification and your selected parameters. The numbers in the green font are auto-calculated numbers. The numbers in the blue font are the design actual selected (used) number.
47. 47. Simulation IndexAll Rights Reserved Copyright (C) Bee Technologies Corporation 2012 47Simulations Folder name1. Application Circuit.......................................................................2. Application Circuit with Time Scaling (tscale =10).........................3. Simulation of Step (1) and (2).....................................................4. Simulation of Step (3) and (4).....................................................5. Simulation of Step (5).................................................................6. Simulation of Step (6) at Vin, max..................................................7. Simulation of Step (6) at Vin, min...................................................8. Simulation of Step (7).................................................................9. Simulation of Step (8).................................................................10. Switching Devices VPEAK and IPEAK at Steady State...................11. Switching Devices VPEAK and IPEAK at Start Up...........................APPCKTAPPCKT_tscaleSTEP1-2STEP3-4STEP5STEP6_INMAXSTEP6_INMINSTEP7STEP8IVPEAK-SSIVPEAK-SULibraries :1. ..¥part¥tb6819afg¥tb6819afg.lib2. ..¥part¥parts.lib