Direct Memory Address with its DMA Controller

1. DIRECT MEMORY
ACCESS
DMA CONTROLLER 8237 INTERFACING
Er. Sulav Paudel | MSc

2. DMA
◦ An I/O technique commonly used for high data transfer.
◦ For example, data transfer between system memory and a floppy disk.
◦ In status check, I/O and interrupt I/O, data transfer is relatively slow
because each instruction needs to be fetched and executed.
◦ In DMA, the MPU release the control of the buses to a device called a
DMA Controller.
◦ The controller manages data transfer between memory and a peripheral
under its control, thus by passing the MPU
Er. Sulav Paudel | MSc

3. DMA
◦ DMA uses two signals – HOLD and HLDA in 8085 microprocessor
◦ HOLD:
 This is an active high signal to 8085 from another master requesting the use
of address and data buses.
 After receiving the HOLD request, the MPU relinquishes the buses in the
following machine cycle.
 All buses are tri-stated and hold acknowledge (HLDA) signal is sent out.
 MPU regains the control of the buses after HOLD goes low.
Er. Sulav Paudel | MSc

4. DMA
◦ HLDA
 This is active high output signal indicating that MPU is relinquishing
control of the buses.
 A DMA Controller uses these signals as if it were a peripheral
requesting the MPU for the control of the buses.
Er. Sulav Paudel | MSc

5. Concept of DMA
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6. Block Diagram of DMA Transfer
Er. Sulav Paudel | MSc

7. DMA Controller
◦ The data transfer technique in which peripherals manage the memory
buses for direct interaction with main memory without involving the
CPU is called direct memory access (DMA).
◦ Using DMA technique large amounts of data can be transferred between
memory and the peripheral without severely impacting CPU
performance.
◦ During the DMA transfer, the CPU is idle and has no control of the
memory buses.
◦ A DMA controller takes over the buses to manage the transfer directly
between the I/O device(s) and main memory.
Er. Sulav Paudel | MSc

8. DMA Controller
◦ The control unit communicates the CPU via data bus and control lines.
◦ The DMA controls/relinquishes the system bus using BR (Bus Request)
and BG (Bus Grant) signals.
◦ DMA operates read and write operations via RD (Read) and WR (Write)
signals.
◦ DMA sends request and acknowledge to I/O devices via DMA request
and DMA acknowledge signals.
◦ The registers in DMA are selected by CPU through the address bus by
enabling DS (DMA Select) and RS (Register Select) inputs.
Er. Sulav Paudel | MSc

9. DMA Controller
◦ All registers in the DMA appear to the CPU as I/O interface registers.
◦ The address register contains an address to specify the desired location
in memory.
◦ It is incremented after each word that is transferred to the memory.
◦ The word count register holds the number of words to be transferred.
◦ It is decremented by one after each word transfer and internally tested
for zero.
Er. Sulav Paudel | MSc

10. DMA Transfer Operation
◦ The DMA request CPU to handle control of buses to the DMA using bus request
(BR) signal.
◦ The CPU grants the control of buses to DMA using bus grant (BG) signal after
placing the address bus, data bus and read and write lines into high impedance
state (which behave like open circuit).
◦ CPU initializes the DMA by sending following information through the data bus.
1. Starting address of memory block for read or write operation.
2. The word count which is the no. of words in the memory block.
3. Control to specify the mode of transfer such as read or write.
4. A control to start the DMA transfer.
Er. Sulav Paudel | MSc

11. DMA Transfer Operation
◦ The DMA takes control over the buses directly interacts with memory
and I/O units and transfers the data without CPU intervention.
◦ When the transfer completes, DMA disables the BR line.
◦ Thus CPU disable BG line, takes control over the buses and return to its
normal operation.
Er. Sulav Paudel | MSc

12. Sequence of DMA Transfer
The sequence of DMA transfer as shown in the previous block diagram can be
explained below:
1. Originally, microprocessor is connected to the memory as shown in figure
above with switches closed for address, data and control buses. When
peripheral wants to transfer data using DMA Transfer, it sends DMA request,
DREQ signal to the DMA controller.
2. If the input (channel) of the DMA controller is unmasked, the DMA controller
will send a hold-request, HRQ signal to the microprocessor HOLD input.
Er. Sulav Paudel | MSc

13. 3. The microprocessor finishes the current machine cycle and floats its
buses, sending out a hold acknowledge signal, HLDA to the DMA
controller.
4. When DMA controller receives HLDA signal, it will send a control
signal which throws the 3 bus switches down to their DMA position.
This disconnects the processor from buses and connects DMA
controller to the buses. Now DMA controller sends out the address
of the byte to the transferred and sends out DMA acknowledge
(DACK) signal to the peripheral device to tell it to get ready to output
the byte.
Er. Sulav Paudel | MSc

14. 5. Then the DMA transfer begins and finally when the data transfer is
complete, the DMA controller unasserted its hold-request signal to
the processor and releases the buses.
Er. Sulav Paudel | MSc

15. 8237 DMA Controller
◦ On chip four independent DMA channels. Number of channels can be
increased by cascading DMA controller chips.
◦ Transfers data between two memory blocks in DMA mode:
 Memory to Memory Transfer
 Memory to I/O Device
 I/O Device to Memory
 I/O Device to I/O Device
Er. Sulav Paudel | MSc

16. 8237 DMA Controller
◦ In memory to memory transfer a single word can be written into all
locations of memory block.
◦ Data transfer rate is very high e.g. 1.6M bytes/second for 8237-2 of 5
Mhz.
◦ Directly expandable to any number of channels. It does not require any
additional chip for cascading. There is no limitations on cascading.
◦ It provides EOP line that is used to terminate DMA operation. This signal
is generated by external hardware.
Er. Sulav Paudel | MSc

17. 8237 DMA Controller
◦ The address of memory is either incremented or decremented after each DMA
cycle depending upon the mode.
◦ DMA can be requested by setting an appropriate bit of request register.
◦ Independent control of DREQ and DACK signal, DREQ and DACK signals can be
initialize either for active high or active low.
◦ Provides compressed timings to improve throughput of the system.
◦ It can compress the transfer time to two cycles(2S).
Er. Sulav Paudel | MSc

18. DMA Data Transfer
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19. Block Diagram of 8237
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20. Signals of 8237 DMA
◦ CLK:
 CLK input line ignored in slave mode.
 In master mode, this signal controls all internal and external DMA
operations.
 The data transfer rate depends upon the frequency of this signal.
 CS:
 In slave mode, this signal is generated by address decoder to select
8287 chip to communication between CPU and 8237.
 In master mode, this signal is ignored.
Er. Sulav Paudel | MSc