B sc e5.2 mp unit 3 interfacing

MP-8085 AND MC
UNIT-3 INTERFACING

INTERFACING : IN and OUT instructions in 8085 Microprocessor:
Mnemonics, Operand Opcode(in HEX) Bytes
IN Port-address DB 2
OUT Port-Address D3 2
In 8085 Instruction set, there are two instructions in 8085 for communication with I/O ports. They are the IN and
OUT instructions. The IN or OUT instruction mnemonics should be followed by an 8-bit port address. Thus we can
have 28 = 256 input ports and 256 output ports are possible in 8085-based microcomputers. IN and OUT both are
2-Bytes instructions.
In case of IN instruction, the current 8-bit content of the PORT# will be made available on to the Accumulator. Let
us suppose with the PORT#, 8 DIP switches are connected. And their states are ON-ON-OFF-ON-ON-ON-OFF-
ON. So after execution of the instruction IN PORT#, the Accumulator content will be 1101 1101.
In case of OUT instruction, the current 8-bit content of the Accumulator will be copied on to the PORT#. Let us
suppose that Accumulator’s initial content is 0101 0101. And with the 8-bit port 8 LEDs are connected. So after
execution of the instruction OUT PORT#, LEDs will have the OF-OFF states .

• Interrupts in 8085 microprocessor
• When microprocessor receives any interrupt signal from peripheral(s) which are
requesting its services, it stops its current execution and program control is
transferred to a sub-routine by generating CALL signal and after executing sub-
routine by generating RET signal again program control is transferred to main
program from where it had stopped.
• When microprocessor receives interrupt signals, it sends an acknowledgement
(INTA) to the peripheral which is requesting for its service.
• Interrupts can be classified into various categories based on different parameters:
• Hardware and Software Interrupts –
When microprocessors receive interrupt signals through pins (hardware) of
microprocessor, they are known as Hardware Interrupts. There are 5 Hardware
Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
• Software Interrupts are those which are inserted in between the program which
means these are mnemonics of microprocessor. There are 8 software interrupts in
8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST
7.

INTERRUPT VECTOR ADDRESS
TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H
Vectored and Non-Vectored Interrupts –
Vectored Interrupts are those which have fixed vector address (starting
address of sub-routine) and after executing these, program control is
transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE

1.For Software interrupts vector addresses are given by:
INTERRUPT VECTOR ADDRESS
RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H
RST 5 28 H
RST 6 30 H
RST 7 38 H

• Non-Vectored Interrupts are those in which vector address is not predefined.
The interrupting device gives the address of sub-routine for these
interrupts. INTR is the only non-vectored interrupt in 8085 microprocessor.
• Maskable and Non-Maskable Interrupts –
Maskable Interrupts are those which can be disabled or ignored by the
microprocessor. These interrupts are either edge-triggered or level-triggered,
so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable
interrupts in 8085 microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both level as
well as edge triggering and is used in critical power failure conditions.
Priority of Interrupts –
When microprocessor receives multiple interrupt requests simultaneously, it
will execute the interrupt service request (ISR) according to the priority of
the interrupts.

• Masking of Interrupts: Masking can be done for four hardware interrupts
INTR, RST 5.5, RST 6.5, and RST 7.5. The masking of 8085 interrupts is done
at different levels. Fig. 13 shows the organization of hardware interrupts in
the 8085.

• The Fig. 13 is explained by the following five points:
• 1.The maskable interrupts are by default masked by the Reset signal. So no
interrupt is recognized by the hardware reset.
• 2. The interrupts can be enabled by the EI instruction.
• 3. The three RST interrupts can be selectively masked by loading the
appropriate word in the accumulator and executing SIM instruction. This is
called software masking.
• 4. All maskable interrupts are disabled whenever an interrupt is recognized.
• 5. All maskable interrupts can be disabled by executing the DI instruction.
• RST 7.5 alone has a flip-flop to recognize edge transition. The DI instruction
reset interrupt enable flip-flop in the processor and the interrupts are
disabled. To enable interrupts, EI instruction has to be executed.

• Instruction for Interrupts –
• Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts
are enabled following the execution of next instruction followed by EI. No
flags are affected. After a system reset, the interrupt enable flip-flop is reset,
thus disabling the interrupts. This instruction is necessary to enable the
interrupts again (except TRAP).
• Disable Interrupt (DI) – This instruction is used to reset the value of enable
flip-flop hence disabling all the interrupts. No flags are affected by this
instruction.
• Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts
(RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate
output data via the Serial Output Data (SOD) line. First the required value is
loaded in accumulator then SIM will take the bit pattern from it.

• Read Interrupt Mask (RIM) – This instruction is used to read the status of the
hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a
byte which defines the condition of the mask bits for the interrupts. It also
reads the condition of SID (Serial Input Data) bit on the microprocessor.

INTERFACING:
• Interface is the path for communication between two components. Interfacing is of
two types, memory interfacing and I/O interfacing.
• Memory Interfacing
• When we are executing any instruction, we need the microprocessor to access the
memory for reading instruction codes and the data stored in the memory. For this,
both the memory and the microprocessor requires some signals to read from and
write to registers.
• The interfacing process includes some key factors to match with the memory
requirements and microprocessor signals. The interfacing circuit therefore should
be designed in such a way that it matches the memory signal requirements with
the signals of the microprocessor.
• IO Interfacing
• There are various communication devices like the keyboard, mouse, printer, etc.
So, we need to interface the keyboard and other devices with the microprocessor
by using latches and buffers. This type of interfacing is known as I/O interfacing.
• Block Diagram of Memory and I/O Interfacing

Block Diagram of Memory and I/O Interfacing

• 8085 Interfacing Pins
• Following is the list of 8085 pins used for interfacing with other devices −
• A15 - A8 (Higher Address Bus)
• AD7 - AD0(Lower Address/Data Bus)
• ALE , RD , WR , READY.
• There are two ways of communication in which the microprocessor can connect
with the outside world.
• Serial Communication Interface
• Parallel Communication interface
• Serial Communication Interface − In this type of communication, the interface gets
a single byte of data from the microprocessor and sends it bit by bit to the other
system serially and vice-a-versa.
• Parallel Communication Interface − In this type of communication, the interface
gets a byte of data from the microprocessor and sends it bit by bit to the other
systems in simultaneous (or) parallel fashion and vice-a-versa.

COMPETABLE ICs OF MP - 8085
• 1. IC-8279 Programmable KBD/Display Controller.
• 2. IC-8257/8237 DMA Controller.
• 3. IC- 8051 Microcontroller.
• 4. IC- 8212 NPPI IO Port.
• 5. IC- 8255 PPI IO Port.
• 6. IC-8253/54 PIT-Programmable Interval Timer.
• 7. IC-8251 Communication Interface.
• 8. IC-8259 Interrupt Controller.
• 9. IC- 8275 CRT Controller.
• 10.IC-8272 Floppy Disc Controller.
• 11.IC-82064 Hard Disc Controller.
• 12.IC-8295 Printer Controller etc.

DATA TRANSFER SCHEMES:
• The data transfer may take place between microprocessor and memory,
microprocessor and I/O devices and memory & I/O devices. Another very
important thing is that we can get very smooth data communication between
microprocessor and memory. Because the same technology is used in the
manufacturing of memory and microprocessor. So it has all most same bus
speed. The main reason for that the speed of the memory is almost
compatible with the speed of 8085 microprocessor. Now the main concern is
for data transfer between the microprocessor and I/O devices. In that case,
the main problems arise due to mismatch of the speed of the I/O devices
• In 8085 microprocessor following data transfer schemes may be considered
for smooth data transfer process. The data transfer schemes of it can
categorized depending upon the capabilities of I/O devices for accepting
serial or parallel data.

• Serial I/O mode transfer
• For these devices and for these above mention reasons serial I/O mode is used. In
serial I/O mode transfer a single bit of data on a single line at a time. For serial I/O
data transmission mode, 8-bit parallel word is converted to a stream of eight serial
bit using parallel-to-serial converter. Similarly, in serial reception of data, the
microprocessor receives a stream of 8-bit one by one. After receiving serial data, it
converted to 8- bit parallel word using serial-to-parallel converter. For this purpose
data transfer schemes of 8085 microprocessor are introduced.
• Parallel data transfer scheme
• Parallel data transfer scheme is faster than serial I/O transfer. In parallel data
transfer mode, 8-bit data send all together with 8 parallel wire. In 8085
microprocessor mainly three types of parallel data transfer scheme we observed.
Those are
• Programmed I/O Data Transfer
• Interrupt Driven I/O Data Transfer
• Direct Memory Access (DMA) Data Transfer.

1.Programmed Data transfer Scheme: In Programmed
data transfer scheme a prgramme stored in memory controles the
data transfer in 8085 MP.It is further classed to synchronous and
Asynchronous and Interrupt driven data transfer.
Synchronous:Synchronous type of data transfer can be used
when the speed of the I/O devices matches with the speed of the
8085 microprocessor. So we need common clock pulse for
established the synchronization between I/O device and
microprocessor. This common clock pulse synchronizes the
microprocessor and the I/O devices. In synchronous type of data
transfer scheme, it has matching of the speed with I/O devices. So it
does not have to wait for the availability of the data. As soon as the
microprocessor issues a signal, it immediately sends data for the
transfer

•The asynchronous type data transfer: The asynchronous data
transfer method is used when the speed of the I/O devices is slower than the speed
of the microprocessor. Because of the mismatch of the speed, the internal timing of
the I/O device is independent from the microprocessor. That is why those two units
can said to be asynchronous to each other. The asynchronous data transfer is
normally implemented using ‘handshaking’ mode.
• In the handshaking mode some signals are exchanged between the I/O device and
microprocessor before the data transfer takes place. Now look at the flow chart
bellow which can describe the total process step wise.
• By this handshaking it has to check the status to the input/output device. Now if it
found the device is ready for the data transfer. Then it performs some simple steps
to complete the task.
• First step of microprocessor is initiates the I/O device to get ready.
• Then status of the I/O device continuously checked by the microprocessor.
• This process remain continues until the I/O device becomes ready.
• After that microprocessor sends instructions to transfer the data.

• Now form this bellow figure, we can see that the microprocessor sends a
ready signal to I/O device. When the device is ready to accept the data, the
I/O device sends an ‘ACK’ (Acknowledge) signal to microprocessor. By sending
ACK, it indicating that the I/O device has acknowledged the ‘Ready’ signal.
Now finally it is ready for the transfer of data.

• Again in bellow figure shows the asynchronous handshaking process to
transfer the data from the I/O device to microprocessor. In this case I/O
device issues the ready signal to microprocessor indicating that I/O device is
ready to send the data to microprocessor. So in response to this signal, the
microprocessor send valid data signal to I/O device and then that data put
on the data bus for the transfer.
•

•Interrupt Driven data transfer scheme: In the programmed
I/O data transfer method, microprocessor is busy for all the time. Because in
this mode, it always checking for the availability of data from the slower I/O
devices. And it also busy in checking if I/O device is ready for the data
transfer or not. In other words, in this data transfer scheme, some of the
microprocessor time is wasted in waiting while an I/O device is getting ready.
To overcome this problem interrupt driven I/O data transfer introduced.
• The interrupt driven I/O data transfer method is very efficient. Because no
microprocessor time is wasted in waiting for an I/O device to be ready. After
checking the I/O device is ready or not. In this interrupt driven I/O data
transfer method, the I/O device informs the microprocessor for the data
transfer. And This can achieved by interrupting the microprocessor. As we
know, the interrupt is hardware facilities provided on the microprocessor.

• Now come to the working process of interrupt driven I/O data transfer. So the
beginning, the microprocessor requesting the I/O device ‘to get ready’. After
that it initiates data transfer. In between this time frame, it continue
executing its original program rather wasting its time by checking the status
of I/O device. Whenever the device is ready to accept or supply data. It send
information to the processor through a control signal. This control signal is
known as interrupt (INTR) signal.
• First step, in response to this interrupt signal, the microprocessor sends back
an interrupt acknowledge signal to the I/O device. By sending
acknowledgement, it indicating that it received the request.
• Second step, then it suspends its job after executing the current instruction.
It saves the contents and status of program counter to stack. And it jumps to
the subroutine program.
• This subroutine program is called Interrupt Service Subroutine (ISS) program.
The ISS stores the status of processor into stack. After that, it start executing
the instruction for the data transfer. Finally, it restores the processor status
and then returns back to main program.

• So in short, we just point out those steps with quick recall.
• A peripheral device send an interrupt request.
• Processor complete the execution of the current instruction.
• Now the processor issued an acknowledgement request.
• The program then branches to Interrupt Service Subroutine (ISS) program.
• The return address is stored in the stack.
• Stored other register contents as per program needs.
• Data transfer takes place under ISS.
• Enabled the interrupt system.
• Loading the return address from stack into program counter (PC).
• The program then returns to the main program.

• Using interrupt driven data transfer scheme, several input/output devices may
connected to microprocessor. Following interrupt request configuration may arise
while interfacing the I/O devices to microprocessor.
• Single Interrupt system. * Multi Interrupt System.
• Single Interrupt System
• When only one interrupt line is available with the microprocessor. And several I/O
devices has to connect. Then the method will known as Single Interrupt System.
• Multi Interrupt System
• When the microprocessor has several interrupt terminals. And one I/O device has to
connect in each interrupt terminal. Then it known as multi interrupt system. Now
some important thing we should remember. In this scheme, the number of I/O
devices to be connected to the interrupt lines should be equal to or less than the
number of interrupt terminals. In this way one device can connected to each level of
interrupt. So when a device interrupts the microprocessor, it immediately knows
which device has interrupted. Such an interrupt scheme also known as vectored
interrupt.

•Direct Memory Access (DMA):
• DMA is a process of communication for data transfer between memory and
input/output, controlled by an external circuit called DMA controller, without
involvement of CPU.
• 8085 MP has two pins HOLD and HLDA which are used for DMA operation.
• First, DMA controller sends a request by making Bus Request (BR) control line
high. When MP receives high signal to HOLD pin, it first completes the
execution of current machine cycle, it takes few clocks and sends HLDA signal
to the DMA controller.
• After receiving HLDA through Bus Grant (BG) pin of DMA controller, the DMA
controller takes control over system bus and transfers data directly between
memory and I/O without involvement of CPU. During DMA operation, the
processor is free to perform next job which does not need system bus.
• At the end of data transfer, the DMA controller terminates the request by
sending low signal to HOLD pin and MP regains control of system bus by
making HLDA low.

• Figure shows the block diagram of a typical DMA controller. The unit communicates
with the MP via the data bus and control lines.
• The registers in the DMA are selected by the MP through the address bus by
enabling the DS (DMA select) and RS (Register Select) inputs. The RD (read) and WR
(write) inputs are bidirectional.
• When the bus grant (BG) input is 0, the MP can communicate with the DMA
registers through the data bus to read from or write to the DMA registers. When
BG=1, the processor does not have control over the system buses and the DMA can
communicate directly with the memory by specifying an address in the address bus
and activating the RD or WR control.
• The DMA controller has three registers: an address register, a word count register
and a control register.
• The address register contains an address to specify the desired location in memory.
The address bits go though bus buffers into the address bus. The address register is
incremented after each word that is transferred to memory.
• The word count register holds the number of words to be transferred. The register
is decremented by one after each word transfer and internally tested for zero.
• The control register specifies the mode of transfer.

•Memory Interfacing in 8085:
• Memory is an integral part of a microprocessor system, and in this section,
we will discuss how to interface a memory device with the microprocessor.
The Memory Interfacing in 8085 is used to access memory quite frequently to
read instruction codes and data stored in memory. This read/write operations
are monitored by control signals. The microprocessor activates these signals
when it wants to read from and write into memory. In the last section we
have already seen the memory read and memory write machine cycles, and
status of the RD, WR and IO/M status signals for read/write operation. In the
following section we will see memory structure and its requirements,
concepts in Memory Interfacing in 8085 and interfacing examples.
• Memory Structure and its Requirements:
• As mentioned earlier, read/write memories consist of an array of registers, in
which each register has unique address. The size of the memory is N x M as
shown in Fig. 4.13 (a) where N is the number of registers and M is the word
length, in number of bits.

• Microprocessor 8085 can access 64Kbytes memory since address bus is 16-
bit. But it is not always necessary to use full 64Kbytes address space. The
total memory size depends upon the application.
• Generally EPROM (or EPROMs) is used as a program memory and RAM (or
RAMs) as a data memory. When both, EPROM and RAM are used, the total
address space 64Kbytes is shared by them.
• The capacity of program memory and data memory depends on the
application.
• It is not always necessary to select 1 EPROM and 1 RAM. We can have
multiple EPROMs and multiple RAMs as per the requirement of
application.
• We can place EPROM/RAM anywhere in full 64 Kbytes address space. But
program memory (EPROM) should be located from address 0000H since
reset address of 8085 microprocessor is 0000H.
• It is not always necessary to locate EPROM and RAM in consecutive
memory For example : If the mapping of EPROM is from 0000H to OFFFH, it
is not must to locate RAM from 1000H. We can locate it anywhere between
1000H and FFFFH. Where to locate memory component totally depends on
the application.

For Memory Interfacing in 8085, following important points are to be kept in mind.
• 1.Microprocessor 8085 can access 64Kbytes memory since address bus is 16-bit. But it is not
always necessary to use full 64Kbytes address space. The total memory size depends upon
the application.
• 2.Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a
data memory. When both, EPROM and RAM are used, the total address space 64Kbytes is
shared by them.
• 3.The capacity of program memory and data memory depends on the application.
• 4.It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs
and multiple RAMs as per the requirement of application.
• 5.We can place EPROM/RAM anywhere in full 64 Kbytes address space. But program
memory (EPROM) should be located from address 0000H since reset address of 8085
microprocessor is 0000H.
• 6.It is not always necessary to locate EPROM and RAM in consecutive memory For example :
If the mapping of EPROM is from 0000H to OFFFH, it is not must to locate RAM from 1000H.
We can locate it anywhere between 1000H and FFFFH. Where to locate memory
component totally depends on the application.

• The memory interfacing requires to :
• Select the chip
• Identify the register
• Enable the appropriate buffer.
• Microprocessor system includes memory devices and I/O devices. It is
important to note that microprocessor can communicate (read/write) with
only one device at a time, since the data, address and control buses are
common for all the devices. In order to communicate with memory or I/O
devices, it is necessary to decode the address from the microprocessor. Due
to this each device (memory or I/O) can be accessed independently. The
following section describes common address decoding techniques.

•Memory interfacing – Problem statement
• Interface a 1kB EPROM and a 2 kB RAM with microprocessor 8085. The
address allotted to 1 kB EPROM should be 2000H to 22FFH. You can assign
the address range of your choice to the 2 kB RAM.
• The first step to solve this problem is to understand the pins of the given
memory chips.
• Pin diagram of memory chips
• RAM and ROM both have same pins, except for WR pin, which is present in
RAM and is not there in a ROM. Let us understand the pins one by one.

• Data pins: Since each memory location stores eight bits, there are eight
data lines D0-D7 connected to the memory chip.
• Address pins: The number of address pins depends on the size of the
memory. In this case, a memory of size 1 kB x 8 will have 210 different
memory locations. Hence, it will have ten address lines A0 to A9. Similarly,
the 2 kB RAM will have 211 different memory locations. So, there are 11
address lines A0-A10.
• CS pin: When this pin is enabled, the memory chip knows that the
microprocessor is talking to it and responds to it accordingly. We need to
generate this signal for each of the chips according to the range of
addresses assigned to them. Basically, we select a chip only when it is
needed. The Chip Select (CS) pin is used for this.
• OE pin: When this active-low output enable pin is enabled, the memory
chip can output the data into the data bus.

• WR pin: Upon activation of this active-low memory write pin, data on the
data bus is written on the memory chip at the location specified by the
address bus.
• VCC and GND pins: These pins serve the purpose of powering the ICs. For
simplicity, we will not show these pins in the diagram.
• There are three types of buses in 8085 – Address bus, data bus, and control
bus. Each of these buses will be connected to the memory chip.
• Connecting Control Signals
• In the memory chips, there are two pins for control signals – OE (Output
Enable) and WR (Memory Write). These will be connected to the control
signals generated using a 3 to 8 decoder. To read about the generation of
control signals, you can read our post on Demultiplexing of Bus and
Generating Control Signals. The circuit for generating control signals is
shown below.

Four control signals are generated when we input the WR, RD and IO/M signals
from the 8085 to the 3:8 decoder – IOR, IOW, MEMR and MEMW. Since we are
dealing with memory, we will just need MEMR and MEMW signals.
While reading from a memory chip, it’s output should be enabled. So, MEMR will
be connected to the OE pin. Similarly, for writing to a memory chip, MEMW will be
connected to the WR pin of the RAM. After completing these two connections, we
are done with the control signals except CS. We will deal with that in a bit.

• Data Bus interfacing
• There are eight lines comprising the data bus of both 8085 and the memory
chips. The interfacing of the data bus is the simplest part. We just connect
corresponding lines (D0-D7 from 8085) to the corresponding pins (D0-D7 of
the memory chip).
• Address bus Interfacing
• We have a 2kB RAM with 11 address lines. So, the first 11 lines of the
address bus of 8085 will be connected to the corresponding address lines of
the 2kB RAM. Similarly, the first 10 lines of the address bus of 8085 will be
connected to the corresponding lines of 1kB EPROM. The remaining address
lines will be used to generate the chip select (CS) signal.
• Generating the chip select signal
• This is a little tricky, but it’s the most important part of solving the problem.
Let us proceed step by step and build up an intuition of how to generate the
chip select signal for a memory of given size and given address range.

• Let us tabulate the starting and ending address of the 1kB EPROM.
• A15 is most significant, and A0 is the least significant bit. The address range
for placing the EPROM is from 2000H to 22FFH (as given in the question.)
Translating these to binary:
• 2000H = 0011 0000 0000 0000
• 22FFH = 0011 0011 1111 1111
• Address bit number : A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0 Starting
address : 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
• Ending Address : 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1
• From the above table, we can observe that ten bits from A0 to A9 are changing. These
ten bits are directly connected to the address lines of the memory chip.
• These ten bits take the value of either 0 or 1 to form addresses. The first address is 00
0000 0000, and the second address is 00 0000 0001, the third is 00 0000 0010 and so on.
The last address will be 11 1111 1111.

• Meanwhile, bits A11 to A15 do not change and don’t have any effect on the
addressing process inside the memory chip. So, we can conclude that the
values of bits A15-A11 (0011 00) given in the above table are in a unique,
unchanging configuration for this memory chip. If even one of these bits
changes, the address won’t belong to this memory chip. So, we can use
these values of A15-A11 to uniquely identify this memory chip, which is
exactly what the CS signal is supposed to do.
• We can say that when A15 = A14 = A11 = A10 = 0 and A13 = A12 = 1, then
our memory chip should be selected. Now, we need to design the logic to
generate the CS signal. The resulting Boolean equation of CS will be:
• CS = Complement of (A15* . A14* . A13 . A12 . A11* . A10*)
• This equation can be implemented using NAND Gate. The final chip select
logic for 1kB EPROM is illustrated below.

Now, we have to generate a chip select signal for the second memory chip, which
is 2kB RAM. The process is quite similar and differs from the previous one in two
ways: The size of the memory is different. So, there are 11 address lines instead of
10.We are not given an address range here. We are given the liberty to decide on
our own.Similar to the previous case, we connect the first 11 address lines of the
8085 microprocessor to the 11 address lines of the 2kB RAM. These bits will take
values of 0 and 1 and will generate 2 * 1024 different addresses. The address bits
A10-A0 will vary from 000 0000 0000 to 111 1111 1111.

• What about the remaining address bits? Well, they don’t have any role in the
addressing of the memory in this 2kB RAM. So, we can fix them to a certain
value without affecting anything. Let’s fix them to 0000 0. Thus, the address
range for this chip becomes 0000 0000 0000 0000 to 0000 0111 1111 1111.
In hexadecimal, the address range will be from 0000H to 07FFH.
• Address bit number
• A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Starting address : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
• Ending Address : 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
• We use a similar technique here. We use the remaining bits A15-A11 to
uniquely identify this chip i.e., to generate chip select signal. So, the boolean
equation will be
• CS = Complement of (A15* . A14* . A13* . A12* . A11*)
• The implementation of this equation using NAND Gate to generate
the CS signal is shown in the following image.

The final circuit
Since we now have the chip select logic and have decided all the connections, it’s
time to finalize the circuit. The entire external memory interfacing circuit can be
broken up into five different parts:
•8085 microprocessor *Demultiplexing of address/data bus *Generation of control
signals *Generation of chip select signals *Memory chips
The images below show the final circuit with all the five parts listed above integrated
into a single circuit. Just the connections are shown in the first diagram. In the
diagram following it, different subsections of the circuit are labeled.

I/O PERIPHERALS INTERFACE
Using I/O devices data can be transferred between the
microprocessor and the outside world. • This can be done in
groups of 8 bits using the entire data bus. This is called
parallel I/O. • The other method is serial I/O where one bit is
transferred at a time using the SID and SOD pins on the
Microprocessor.
Types of Parallel Interface • There are two ways to interface
8085 with I/O devices in parallel data transfer mode: –
* Memory Mapped IO * IO Mapped IO

Memory Mapped IO • It considers them like any other
memory location. – They are assigned a 16-bit address
within the address range of the 8085. – The exchange of
data with these devices follows the transfer of data with
memory. The user uses the same instructions used for
memory.
IO Mapped IO • It treats them separately from memory. –
I/O devices are assigned a “port number” within the 8-bit
address range of 00H to FFH. – The user in this case would
access these devices using the IN and OUT instructions
only.

IO mapped IO V/s Memory Mapped IO:
•IO is treated as memory. • 16-bit addressing. • More
Decoder Hardware. • Can address 216=64k locations.
• Less memory is available. IO Mapped IO • IO is
treated IO. • 8- bit addressing. • Less Decoder
Hardware. • Can address 28=256 locations. • Whole
memory address space is available.

The interfacing of output devices
• Output devices are usually slow. • Also, the output is
usually expected to continue appearing on the output device
for a long period of time. • Given that the data will only be
present on the data lines for a very short period
(microseconds), it has to be latched externally.To do this the
external latch should be enabled when the port’s address is
present on the address bus, the IO/M signal is set high and
WR is set low. • The resulting signal would be active when
the output device is being accessed by the microprocessor. •
Decoding the address bus (for memory-mapped devices)
follows the same techniques discussed in interfacing

Interfacing of Input Devices
• The basic concepts are similar to interfacing of output
devices. • The address lines are decoded to generate a signal
that is active when the particular port is being accessed. • An
IORD signal is generated by combining the IO/M and the RD
signals from the microprocessor.
Interfacing of Input Devices • A tri-state buffer is used to
connect the input device to the data bus. • The control
(Enable) for these buffers is connected to the result of
combining the address signal and the signal IORD.

I/O Peripherals Interface • The objective of interfacing I/O
peripherals: – is to obtain information or results from process. – to store,
process or display. • The instructions IN and OUT perform this operation. •
The following examples shows the process of instruction: 2050 D3 OUT 01H
2051 01

Figure 2 shows one of the way to decode address lines to obtain
output address 01H. • The line address A7 -A0 is connected to eight
NAND gates function as decoder. • The line A0 is connected directly,
A7 -A1 are connected through inverter gates. • The G2 gate is
combined with gate G1 and IO/W control signal to generate select
signal I/O whenever both signals are active low.
Multiple output address, I/O interface • Figure 2 have shown the
technique to decode I/O output address in absolute decoding
technique. • There is another technique which is cost saving -
partial decoding. • This technique gives the flexibility to user as to
use more than one addresses to one output or input device.
Multiple output address, I/O interface shown in fig below.

Multiple output address, I/O interface • The address
lines A1 and A0 are unused. • Depending on the logic
input given at address lines A1 and A0; – the output
addresses: 00h, 01h, 02h or 03h, which refer to the
same output device. • The multiple address is normally
used in a small system; – OK if those addresses are not
being used by any other system, input or output
devices.
Input Interface shown in figure below for IN FFH

The assembly instruction for that circuit in fig. 4 is IN
FFH. • Note: FFH = 1111 1111 binary • The line address
is decoded using NAND gates. • When address A7 -A0
is active high (FFH), the output of NAND gate will have
an active low signal and then combined with control
signals IOR at G2 . • Suppose the μp run the IN FFH
instruction, data at DIP switches will be placed at data
bus and copied to accumulator.

Circuit in figure 5 decode input and output device at
once using 3-to-8 decoder and four input NAND gates.
• The address lines A2 , A1 and A0 are used as inputs
to decoder, and the remaining line address A7 ke A3 is
used to enable the decoder chip. • The decoder has
eight output; therefore we can use the decoder to
address eight kind of input and output devices.
: SEVEN SEGMENT DISPLAY OUTPUT INTERFACE :
Below figure shows output display interface.

Seven segment display output
• Fig 6 shows two different type of 7-segment display;
common cathode and common anode.
• 7-segment display consists of a few LEDs and
are arranged physically as shown in figure 7a.
• It has seven segment from A to G that
normally connected to data bus D0 to D6 respectively.
• If decimal point is used, D7 will be connected
to DP; and left unconnected if it is unused.

Seven segment display output interface.

Fig. 7 shows the example to interface seven segment display
and address decoder with an address of FDH. • The common
anode display is used therefore 0 logic is needed to activate
the segment. • Suppose to display number 4 at seven
segment display, therefore the segment F, G, B and C have to
be activated. • Follows are the instructions to execute it: –
MVI A, 66H [DISPLAY : 4 ]
OUT FDH
Data lines: D7 D6 D5 D4 D3 D2 D1 D0
Bits : X 1 1 0 0 1 1 0 = 66 H
Segments: NC G F E D C B A

INTRFACING DEVICES :
• 1. I/O PORTS: It is the device interface between the I/p device or
o/p device or both.There are two types : Non programmable
peripheral interface(NPPI) Ex:IC 8212 NPPI and Programable
peripheral interface(PPI) Ex:IC 8255 PPI .
• PROGRAMMABLE PERIPHERAL INTERFACE ic 8255:
• PPI 8255 is a general purpose programmable I/O device designed
to interface the CPU with its outside world such as ADC, DAC,
keyboard etc. We can program it according to the given condition.
It can be used with almost any microprocessor.
• It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B
and PORT C. We can assign different ports as input or output
functions.PORTC(8)=PORTC upper(4)+PORTC Lover(4).

It consists of 40 pins and operates in +5V regulated power supply. Port
C is further divided into two 4-bit ports i.e. port C lower and port C
upper and port C can work in either BSR (bit set rest) mode or in mode
0 of input-output mode of 8255. Port B can work in either mode or in
mode 1 of input-output mode. Port A can work either in mode 0, mode
1 or mode 2 of input-output mode.It has two control groups, control group
A and control group B. Control group A consist of port A and port C upper.
Control group B consists of port C lower and port B.
Depending upon the value if CS’, A1 and A0 we can select different ports in
different modes as input-output function or BSR. This is done by writing a
suitable word in control register (control word D0-D7).

CS’ A1 A0 SELECTION ADDRESS
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control Register 83 H
1 X X No Seletion X

Pin diagram –
•PA0 – PA7 – Pins of port A
•PB0 – PB7 – Pins of port B
•PC0 – PC7 – Pins of port C
•D0 – D7 – Data pins for the
•transfer of data
•RESET – Reset input
•RD’ – Read input
•WR’ – Write input
•CS’ – Chip select
•A1 and A0 – Address pins

Operating modes –
1.Bit set reset (BSR) mode –
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C
bits are used for set or reset.

The most significant bit (D7) is 1 for the I/O mode and 0 for the BSR mode. D6 &
D5It is used to set the port A mode.
•D4 is used to tell whether port A is taking input or displaying the result. If it is 1 then it
is taking input otherwise displaying output.D3 is used to tell whether port C higher bits
is taking input or displaying the result. If it is 1 then it is taking input otherwise
displaying output.D2 tells the mode of port B. If it is 0 then port B is in m0 mode
otherwise in m1 mode.D1 is used to tell whether port B is taking input or displaying
the result. If it is 1 then it is taking input otherwise displaying output.D0 is used to tell
whether port C lower bits is taking input or displaying the result. If it is 1 then it is
taking input otherwise displaying output.When 8255 microprocessor is reset, it will
clear the control word register contents, setting all the ports to input mode.

Input-Output mode –
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further
divided into three modes:

•Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input
function or simple output function. In this mode there is no interrupt handling
capacity.
•Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or
port B can work as simple input port or simple output port, and port C bits are used
for handshake signals before actual data transmission. It has interrupt handling
capacity and input and output are latched.Example: A CPU wants to transfer data to
a printer. In this case since speed of processor is very fast as compared to relatively
slow printer, so before actual data transfer it will send handshake signals to the
printer for synchronization of the speed of the CPU and the peripherals.

Mode 2 – Bi-directional data bus mode. In this mode only port A
works, and port B can work either in mode 0 or mode 1. 6 bits port
C are used as handshake signals. It also has interrupt handling
capacity.

PROGRAMMABLE INTERVAL TIMER : IC 8253
• The Intel 8253 is a programmable counter / timer chip designed for
use as an Intel microcomputer peripheral. It uses nMOS technology
with a single +5V supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a counter
rate up to 2 MHz. All modes of operation are software
programmable.
The 82C54 is pin compatible with the HMOS 8254, and is a superset
of the 8253.
Six programmable timer modes allow the 82C54 / 8253 to be used
as an event counter, elapsed time indicator, programmable one-shot,
and in many other applications.

Features of 8253 / 54
The most prominent features of 8253/54 are as follows −
•It has three independent 16-bit down counters.
•It can handle inputs from DC to 10 MHz.
•These three counters can be programmed for either binary or BCD
count.
•It is compatible with almost all microprocessors.
•8254 has a powerful command called READ BACK command, which
allows the user to check the count value, the programmed mode, the
current mode, and the current status of the counter.

8254 Architecture: The architecture of 8254 looks as follows −

The timer has three counters, numbered 0 to 2.[5] Each channel can be programmed
to operate in one of six modes. Once programmed, the channels operate
independently.[1] Each counter has two input pins – "CLK" (clock input) and "GATE" –
and one pin, "OUT", for data output. The three counters are 16-bit down counters
independent of each other, and can be easily read by the CPU.[6]
•Data bus buffer contains the logic to buffer the data bus between the microprocessor
and the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is
the MSB.Read/write logic has 5 pins, which are listed below. The "X" denotes X is an
active low signal.
•RD: read signal
• WR: write signal
• CS: chip select signal * A0, A1: address lines
Operation mode of the PIT is changed by setting the above hardware signals. For
example, to write to the Control Word Register, one needs to
set CS=0, RD=1, WR=0, A1=A0=1. The control word register contains the
programmed information which will be sent (by the microprocessor) to the device. It
defines how each channel of the PIT logically works. Each access to these ports
takes about 1 µs.

To initialize the counters, the microprocessor must write a control word
(CW) in this register. This can be done by setting proper values for the
pins of the Read/Write Logic block and then by sending the control word
to the Data/Bus Buffer block.
The control word register contains 8 bits, labeled D7..D0 (D7 is
the MSB). The decoding is somewhat complex. Most values set the
parameters for one of the three counters:The most significant two bits (if
not 11) select the counter register the command applies to.The next two
bits (if not 00) select the format that will be used for subsequent
read/write access to the counter register. This is commonly set to a
mode where accesses alternate between the least-significant and most-
significant bytes. One difference between the 8253 and 8254 is that the
former had one internal bit which affected both reads and writes, so if
the format was set to 2-byte, a read of the lsbyte would cause a
following write to be directed to the msbyte.

The 8254 used separate bits for reads and writes.The next three bits
select the mode that the counter will operate in.The least significant bit
selects whether the counter will operate in binary or BCD. (BCD
counting almost never used and may not be implemented properly in
emulators or southbridges.)
However, there are two other forms:
•Latch the count for a given timer. The next read will, rather than
returning the counter value at the moment of the read, return the
counter value at the moment of the latch command. After the read
completes, later reads will return the current counter. When the latch
command is used, the mode and BCD status are not changed.
•(8254 only) Latch the status and/or count for multiple timers. This
allows multiple simultaneous latch commands using a bitmap. Also, the
current channel configuration may be read back in addition to the count.

8253/54 Pin Description : Here is the pin diagram of 8253/54 −

In the above figure, there are three counters, a data bus buffer, Read/Write control
logic, and a control register. Each counter has two input signals - CLOCK & GATE,
and one output signal - OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions −
•Programming the modes of 8253/54.
•Loading the count registers.
•Reading the count values.
Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the
peripheral I/O mode, the RD and WR signals are connected to IOR and IOW,
respectively. In the memorymapped I/O mode, these are connected to MEMR and
MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54,
and CS is tied to a decoded address. The control word register and counters are
selected according to the signals on lines A0 & A1.

A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection
Control Word Register
This register is accessed when lines A0 & A1 are at logic 1. It is used to
write a command word, which specifies the counter to be used, its mode,
and either a read or write operation. Following table shows the result for
various control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation

Counters: Each counter consists of a single, 16 bit-down counter, which
can be operated in either binary or BCD. Its input and output is
configured by the selection of modes stored in the control word register.
The programmer can read the contents of any of the three counters
without disturbing the actual count in process.8253/54 can be operated in 6
different modes. In this chapter, we will discuss these operational modes.
Mode 0 ─ Interrupt on Terminal Count: It is used to generate an interrupt to the
microprocessor after a certain interval.Initially the output is low after the mode
is set. The output remains LOW after the count value is loaded into the counter.
The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero and the output goes HIGH and will remain
high until it reloads a new count.
The GATE signal is high for normal counting. When GATE goes low, counting is
terminated and the current count is latched till the GATE goes high again.

Mode 1 – Programmable One Shot
•It can be used as a mono stable multi-vibrator.
•The gate input is used as a trigger input in this mode.
•The output remains high until the count is loaded and a trigger
is applied.
Mode 2 – Rate Generator
•The output is normally high after initialization.
•Whenever the count becomes zero, another low pulse is
generated at the output and the counter will be reloaded.
Mode 3 – Square Wave Generator
•This mode is similar to Mode 2 except the output remains low
for half of the timer period and high for the other half of the
period.

Mode 4 − Software Triggered Mode
•In this mode, the output will remain high until the timer has counted to
zero, at which point the output will pulse low and then go high again.
•The count is latched when the GATE signal goes LOW.
•On the terminal count, the output goes low for one clock cycle then
goes HIGH. This low pulse can be used as a strobe.
Mode 5 – Hardware Triggered Mode
•This mode generates a strobe in response to an externally generated
signal.
•This mode is similar to mode 4 except that the counting is initiated by a
signal at the gate input, which means it is hardware triggered instead of
software triggered.
•After it is initialized, the output goes high.
•When the terminal count is reached, the output goes low for one clock
cycle.

DAC -USING OP-AMP AND MP 8085:
• DAC INTERFACE In many applications, the microprocessor has to produce
analog signals for controlling certain analog devices. Basically the
microprocessor system can produce only digital signals. In order to convert
the digital signal to analog signal a Digital-to-Analog Converter. (DAC) has to
be employed. The DAC will accept a digital (binary) input and convert to
analog voltage or current. Every DAC will have "n" input lines and an analog
output. The DAC require a reference analog voltage (Vref) or current (Iref)
source. The smallest possible analog value that can be represented by the n-
bit binary code is called resolution. The resolution of DAC with n-bit binary
input is 1/2n of reference analog value. Every analog output will be a
multiple of the resolution. In some converters the input reference analog
signal will be multiplied or divided by a constant to get full scale value. Now
the resolution will be 1/2n of full scale value. For example, Consider an 8-bit
DAC with reference analog voltage of 5 volts. Now the resolution of the DAC
is (1/28) x 5 volts. The 8-bit digital input can take, 28 = 256 different values.
The analog values for all possible digital input are as shown in table below.

The maximum input digital signal will have an analog value which is
equal to reference analog value minus resolution. The digital-to-
analog converters can be broadly classified into three categories, and
they are • Current output • Voltage output • Multiplying type The
current output DAC provides an analog current as output signal. In
voltage output DAC, the analog current signal is internally converted
to voltage signal. In multiplying type DAC, the output is given by the
product of the input signal and the reference source and the product
is linear over a broad range. Basically, there is not much difference
between these three types and any DAC can be viewed as
multiplying DAC. Typical DAC circuit: The basic components of a DAC
are resistive network with appropriate values, switches, a reference
source and a current to voltage converter as shown in figure below.

The switches in the circuit of figure above can be transistors which connects the
resistance either to ground or Vref. The resistors are connected in such a way that for any
number of inputs, the total current is in binary proportion. The operational amplifier
converts the current to a voltage signal V0, which can be calculated from the following
equation. The circuit of figure shown above can be modified as 8-bitDAC, by increasing
the number of R/2R ladder. For an 8-bit DAC the output voltage is given by

The time required for converting the digital signal to analog signal is called
conversion time. It depends on the response time of the switching transistors
and the output amplifier. If the DAC is interfaced to microprocessor then the
digital data (Signal) should remain at the input of DAC, until the conversion is
complete. Hence to hold the data a latch is provided at the input of DAC.
The Digital-to-Analog converters compatible to microprocessors are available with or without
internal latch and I to V converting amplifier. The AD558 of Analog Devices is an example of 8-
bit DAC with an internal latch and I to V converting amplifiers. The output of AD558 is an
analog voltage signal. The AD558 can be directly interfaced to 8085 microprocessor

bus and it requires only two control signals: Chip Select (CS) and
Chip Enable (CE). [No handshake signals are necessary for interfacing
a DAC. The time between loading two digital data to DAC is
controlled by software time delay]. The DAC0808 of National
Semiconductor Corporation is an example of 8-bit DAC without
internal latch and I to V converting amplifier. The internal block
diagram and the pin configuration of DAC0808 are shown in figure
below.The DAC0800 can be interfaced to 8085 system through an 8-
bit latch as shown in figure below. The chip select (CS) signal from
the decoder of the microprocessor system is delayed and inverted to
clock the latch. If the DAC is memory mapped then the CS is from
memory decoder. If the DAC is I/O mapped then CS is from I/O
decoder.

The processor sends an address, which is decoded by
decoder in the microprocessor system to produce chip select
signal. Then the processor sends a digital data to latch. The
buffer and inverter will produce sufficient delay for CS signal
so that, the latch is clocked only after the data is arrived at
the input lines of the latch. When the latch is clocked the
digital data is send to DAC. The DAC will produce a
corresponding current signal, which is converted to voltage
signal by the op-amp 741. The typical settling time of
DAC0800 is 150nsec. Therefore the processor need not wait
for loading next data.
* * * * * * * * * * * * * * * THE END * * * * * * * * * * * * *

B sc e5.2 mp unit 3 interfacing

B sc e5.2 mp unit 3 interfacing

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to B sc e5.2 mp unit 3 interfacing

Similar to B sc e5.2 mp unit 3 interfacing (20)

More from MahiboobAliMulla

More from MahiboobAliMulla (20)

Recently uploaded

Recently uploaded (20)

B sc e5.2 mp unit 3 interfacing