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INTERRUPTS OF 8086 MICROPROCESSOR

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The Presentation Contains Information on:-

*INTERRUPTS
*TYPES(SOFTWARE AND HARDWARE)
*PURPOSES
*INTERRUPT VECTOR TABLE
*TYPE 0,1,2,.....18

Published in: Engineering, Technology
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INTERRUPTS OF 8086 MICROPROCESSOR

  1. 1. • An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal) OR • A Software-generated CALL (internally derived from the execution of an instruction or by some other internal event
  2. 2.  An interrupt is used to cause a temporary halt in the execution of program.  The meaning of ‘interrupts’ is to break the sequence of operation.  While the Microprocessor is executing a program, an ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). • After executing ISR, IRET returns the control back again to the main program. Interrupt processing is an alternative to polling.
  3. 3. The keyboard controller can hold only a single keystroke. Therefore, the keyboard controller must be freed before the next keystroke arrives. The keystroke is passed to the CPU by putting it in the keyboard buffer. So, the keyboard controller keeps on passing the keystroke input to the CPU, but how does the CPU attend to it? The CPU is not at the disposal of the keyboard controller; it is usually busy doing several other operations. So, we need some mechanism to indicate to the CPU that a keystroke has arrived. How is this done? There are two approaches to making sure that the CPU pays attention:
  4. 4.  The CPU executes other program, as soon as a key is pressed, the Keyboard generates an interrupt. The CPU will response to the interrupt – read the data. After that returns to the original program. So by proper use of interrupt, the CPU can serve many devices at the “same time”
  5. 5. The Purpose of Interrupts...
  6. 6. Interrupts are useful when interfacing I/O devices at relatively low data transfer rates, such as keyboard inputs. Interrupt processing allows the processor to execute other software while the keyboard operator is thinking about what to type next. When a key is pressed, the keyboard encoder debounces the switch and puts out one pulse that interrupts the microprocessor.
  7. 7. – a time line shows typing on a keyboard, a printer removing data from memory, and a program executing – the keyboard interrupt service procedure, called by the keyboard interrupt, and the printer interrupt service procedure each take little time to execute
  8. 8. TYPES OF INTERRUPT  SOFTWARE INTERRUPTS: There are instructions in 8086 which cause an interrupt. • INT instructions with type number specified. • INT 3, Break Point Interrupt instruction. • INTO, Interrupt on overflow instruction.  HARDWARE INTERRUPTS: The primary sources of interrupts, however, are the PCs timer chip, keyboard, serial ports, parallel ports, disk drives, CMOS real- time clock, mouse, sound cards, and other peripheral devices.
  9. 9. The interrupt vector table contains 256 four byte entries,containg the CS:IP Interrupt vectors for each of the 256 possible interrupts. The table is used to locate the interrupt service routine addresses for each of those interrupts. The Interrupt vector table is located in the first 1024 bytes of memory at addresses 000000H-0003FFH.It contains the address(segment and offset)of the interrupt service provider
  10. 10. The interrupt vector table for the microprocessor and (b) the contents of an interrupt vector. – the first five interrupt vectors are identical in all Intel processors – Intel reserves the first 32 interrupt vectors – the last 224 vectors are user-available – each is four bytes long in real mode and contains the starting address of the interrupt service procedure. – the first two bytes contain the offset address – the last two contain the segment address
  11. 11. TYPE 0 The divide error : whenever the results from a division overflows or an attempt is made to divide by zero.
  12. 12. Type 2 The non-maskable interrupt occurs when a logic 1 is placed on the NMI input pin to the microprocessor. non- maskable—it cannot be disabled
  13. 13. Type 3 A special one-byte instruction (INT 3) that uses this vector to access its interrupt-service procedure. often used to store a breakpoint in a program for debugging
  14. 14. TYPE 4 Overflow is a special vector used with the INTO instruction. The INTO instruction interrupts the program if an overflow condition exists.
  15. 15. TYPE 5 The BOUND instruction compares a register with boundaries stored in the memory. If the contents of the register are greater than or equal to the first word in memory and less than or equal to the second word, no interrupt occurs because the contents of the register are within bounds. if the contents of the register are out of bounds, a type 5 interrupt ensues as reflected by the overflow flag (OF)
  16. 16. Type 7 The coprocessor not available interrupt occurs when a coprocessor is not found, as dictated by the machine status word (MSW or CR0) coprocessor control bits. if an ESC or WAIT instruction executes and no coprocessor is found, a type 7 exception or interrupt occurs
  17. 17. Type 8 A double fault interrupt is activated when two separate interrupts occur during the same instruction.
  18. 18. In computing, a double fault is a serious type of error that occurs when a central processing unit (CPU) cannot adequately handle a certain type of system event that requires the CPU’s immediate attention. Double faults may cause computer crashes and error messages, automatic restarting of the machine, and the loss of any unsaved data. They are often caused by problems in the computer’s hardware such as a bad memory module or overheating CPU.
  19. 19. Type 9 The coprocessor segment overrun occurs if the ESC instruction (coprocessor opcode) memory operand extends beyond offset address FFFFH in real mode.
  20. 20.  Type 10 An invalid task state segment interrupt occurs in the protected mode if the TSS is invalid because the segment limit field is not 002BH or higher. usually because the TSS is not initialized  Type 11 The segment not present interrupt occurs when the protected mode P bit (P = 0) in a descriptor indicates that the segment is not present or not valid.
  21. 21. • Type 12 A stack segment overrun occurs if the stack segment is not present (P = 0) in the protected mode or if the limit of the stack segment is exceeded.
  22. 22. Type 13 The general protection fault occurs for most protection violations in 80286–Core2 in protected mode system. These errors occur in Windows as general protection faults. A list of these protection violations follows.
  23. 23. • Type 13 PROTECTION VIOLATIONS o (a) Descriptor table limit exceeded o (b) Privilege rules violated o (c) Invalid descriptor segment type loaded o (d) Write to code segment that is protected o (e) Read from execute-only code segment o (f) Write to read-only data segment o (g) Segment limit exceeded o (h) CPL = IOPL when executing CTS, HLT, LGDT, LIDT, LLDT, LMSW, or LTR o (i) CPL > IOPL when executing CLI, IN, INS, LOCK, OUT, OUTS, and STI (cont.)
  24. 24. Type 14 Page fault interrupts occur for any page fault memory or code access in 80386, 80486, and Pentium–Core2 processors. Type 16 Coprocessor error takes effect when a coprocessor error (ERROR = 0) occurs for ESCape or WAIT instructions for 80386, 80486, and Pentium–Core2 only.
  25. 25. Type 17 Alignment checks indicate word and double word data are addressed at an odd memory location (or incorrect location, in the case of a double word). interrupt is active in 80486 and Pentium–Core2
  26. 26. Type 18 A machine check activates a system memory management mode interrupt in Pentium– Core2.

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