interrupts,With suitable diagram explain the working of 8255A.

1. MINI PROJECT
Submitted By:
Ran sher(1814110)
1
National Institute of Technology, Silchar

2. CONTENTS
CONTENTS
 (a) With suitable diagram explain the
working of 8255A.
 (b) INTR , interrupts.
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3. Introduction:
 Any application of Microprocessor Based system Requires
the transfer of data between external circuitry to the
Microprocessor and Microprocessor to the External
circuitry.
 User can give information (i.e. input) to the
 User can give information (i.e. input) to the
Microprocessor using keyboard and user can see the result
or output information from the Microprocessor with the
help of display.
 Hence interfacing is used to exchange information between
two different applications/devices.
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4. Memory Mapped I/O:
 Device address is of 16 Bit, means A0 to A15 lines are used
to generate device address.
 MEMR and MEMW control signals are used to control read
and write I/O operations.
 Data transfer is between Any register and I/O device.
 Data transfer is between Any register and I/O device.
 Maximum number of I/O devices are 65536.
 Decoding 16 bit address may requires more hardware.
 For e.g. MOV R M, ADD M,CMP M etc.
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5. I/O mapped I/O:
 Device address is of 8 Bit, means A0 to A7 or A8 to A15 lines
are used to generate device address.
 IOR and IOW control signals are used to control read and
write I/O operations.
 Data transfer is between Accumulator and I/O device.
 Maximum number of I/O devices are 256.
 Decoding 16 bit address may requires less hardware. For e.g.
IN, OUT etc.
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6. Interfacing in memory mapped I/O:
Interfacing in I/O mapped I/O
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7. 8255 PPI:
 The INTEL 8255 is a 40 pin IC having total 24 I/O pins. consisting
of 3 numbers of 8 –bit parallel I/O ports (i.e. PORT A, PORT
B,PORT C).
 The ports can be programmed to function either as a input port or
as a output port in different operating modes.
It requires 4 internal addresses and has one logic LOW chip select
 It requires 4 internal addresses and has one logic LOW chip select
pin.
 Its main functions are to interface peripheral devices to the
microprocessor.
 Basically used for parallel data transfer. operates in mainly two
modes.
 Bit Set Reset Mode (BSR Mode).
 I/O Mode.
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8. 8255 Block Diagram:
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9. Functions of Blocks:
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10. Pin diagram:
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11. Functions of Pins:
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12. Functions of Pins:
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13. Functions of Pins:
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14. Operating modes of 8255:
• There are two main operational modes of 8255:
• Input/output (I/O) mode,
• Bit set/reset mode (BSR Mode).
• I/O mode again classified into three types
(1) Mode 0 (2) Mode 1 (3) Mode 2.
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(1) Mode 0 (2) Mode 1 (3) Mode 2.

15. Mode 0:
• In this mode, the ports can be used for simple
input/output operations without handshaking.
• If both port A and B are initialized in mode 0, the two
halves of port C can be either used together as an
additional 8-bit port, or they can be used as individual 4-
bit ports.
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• Since the two halves of port C are independent, they may
be used such that one-half is initialized as an input port
while the other half is initialized as an output port.
• The mode 0 has following features:
• O/p are latched.
• I/p are buffered not latched.
• Port do not have handshake or interrupt capability.

16. Mode 1:
• When we wish to use port A or port B for handshake
(strobbed) input or output operation, we initialize that port
in mode 1.
• For port B in this mode (irrespective of whether is acting as
an input port or output port), PC0, PC1 and PC2 pins
function as handshake lines.
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function as handshake lines.
• The mode 1 has following features:
• Two ports i.e. port A and B can be use as 8-bit i/o port.
• Each port uses three lines of port c as handshake signal and
remaining two signals can be function as i/o port.
• Interrupt logic is supported.
• Input and Output data are latched.

17. Mode 2:
• Only group A can be initialized in this mode.
• Port A can be used for bidirectional handshake data transfer.
This means that data can be input or output on the same
eight lines (PA0 -PA7).
• Pins PC3 -PC7 are used as handshake lines for port A.
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• The remaining pins of port C (PC0 -PC2) can be used as
input/output lines if group B is initialized in mode 0.
• In this mode, the 8255 may be used to extend the system bus
to a slave microprocessor.

18. Interrupts in 8085 microprocessor
When microprocessor receives any interrupt signal from peripheral(s) which
are requesting its services, it stops its current execution and program control is
transferred to a sub-routine by generating CALL signal and after executing sub-
routine by generating RET signal again program control is transferred to main
program from where it had stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement
(INTA) to the peripheral which is requesting for its service.
Interrupts can be classified into various categories based on different
parameters:
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parameters:
Hardware and Software Interrupts –
•When microprocessors receive interrupt signals through pins (hardware) of
microprocessor, they are known as Hardware Interrupts. There are 5 Hardware
Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP
•Software Interrupts are those which are inserted in between the program
which means these are mnemonics of microprocessor. There are 8 software
interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4,
RST 5, RST 6, RST 7.

19. Vectored and Non-Vectored Interrupts –
Vectored Interrupts are those which have fixed vector address (starting
address of sub-routine) and after executing these, program control is
transferred to that address.
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20. •Maskable and Non-Maskable Interrupts –
Maskable Interrupts are those which can be disabled or ignored by the
microprocessor. These interrupts are either edge-triggered or level-triggered, so
they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in
8085 microprocessor.
•Non-Maskable Interrupts are those which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well
as edge triggering and is used in critical power failure conditions.
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Priority of Interrupts –
When microprocessor receives multiple interrupt requests simultaneously, it will
execute the interrupt service request (ISR) according to the priority of the
interrupts.

21. Instruction for Interrupts –
Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts
are enabled following the execution of next instruction followed by EI. No flags
are affected. After a system reset, the interrupt enable flip-flop is reset, thus
disabling the interrupts. This instruction is necessary to enable the interrupts
again (except TRAP).
Disable Interrupt (DI) – This instruction is used to reset the value of enable
flip-flop hence disabling all the interrupts. No flags are affected by this
instruction.
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instruction.
Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts
(RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate
output data via the Serial Output Data (SOD) line. First the required value is
loaded in accumulator then SIM will take the bit pattern from it.
Read Interrupt Mask (RIM) – This instruction is used to read the status of
the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A
register a byte which defines the condition of the mask bits for the interrupts. It
also reads the condition of SID (Serial Input Data) bit on the microprocessor.

22. THANK YOU
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THANK YOU