pipelining in assembly language and how it is implementing and hazards occur in pipelining and how these hazards are solve................

1. PIPELINING AND HAZARDS

2. WHAT IS PIPELINING?
 Definition: A Pipeline is a series of stages, where
some work is done at each stage. The work is not
finished until it has passed through all stages.
 It is a technique used in advanced microprocessors
where the microprocessor begins executing a
second instruction before the first has been
completed.
 Pipeline is commonly known as an assembly line
operation.

3. WHY PIPELINING?
 With pipelining, the computer architecture allows
the next instructions to be fetched while the
processor is performing arithmetic operations,
holding them in a buffer close to the processor until
each instruction operation can performed.

4. HOW PIPELINING IS IMPLEMENTED?
 The pipeline is divided into segments and each segment can execute it
operation concurrently with the other segments. Once a segment
completes an operations, it passes the result to the next segment in the
pipeline and fetches the next operations from the preceding segment.

5. IMPLEMENTATION OF PIPELINING
1. .data
2. .text
3. li $t1,4
4. li $t2,6
5. li $t3,8
1. sub $t0, $t1, $t2
2. and $t4, $t0, $t3 depends on $t0
3. or $t3, $t1, $t4 depends on $t4

6. Continued
 Example 2:
 .data
 a: .word 2
 b1: .word 3
 .text
 lw $t0, a
 Lw $t1, b1
 add, $t0, $t0, $t1

7. WHAT ARE HAZARDS?
 Hazards are situations that prevent the next
instruction in the instruction stream from executing
in its designated clock cycle. Hazards reduce the
performance from the ideal speedup gained by
pipelining.

8. TYPES OF HAZARDS
There are three different types.
Structural Hazards – Can all stages can be
executed in parallel?
Data Hazards – One instruction might depend on
result of a previous instruction
Control Hazards – fetch cannot continue because
it does not know the outcome of an earlier
branch

9. DATA HAZARDS
 Data hazards occur when the pipeline must be stalled
because one step must wait for another to complete.
 In a computer pipeline, data hazards arise from the
dependence of one instruction on an earlier one that is still in
the. For example, suppose we have instruction
 add $s0, $t0, $t1
 sub $t2, $s0, $t3

10. DATA HAZARDS
Cycle1 Cycle2 Cycle3 Cycle4 Cycle 5 Cycle 6
Add $r3 , $r1 , $r2 Fetch Decode Execute Access
M
Store
Add $r4 , $r3 , $r4 Fetch Decode Execute Access
M
Store
Add $r5 , $r3 , $r4 Fetch Decode Execute Access
M

11. IMPLEMENTATION OF DATA HAZARDS

12. DATA HAZARDS SOLUTION
 The primary solution is based on the observation that we
don’t need to wait for the instruction to complete before
trying to resolve the data hazard. For the code sequence
above, as soon as the ALU creates the sum for the add, we
can supply it as an input for the subtract. Adding extra
hardware to retrieve the missing item early from the internal
resources is called forwarding or bypassing.

13. STRUCTURAL HAZARDS
The first hazard is called a “structural hazard”. It means
that the hardware cannot support the combination of
instructions that we want to execute in the same clock
cycle.
Instruction fetching and data fetching is being done in
same cycle.

14. STRUCTURAL HAZARDS
Cycle1 Cycle2 Cycle3 Cycle4 Cycle 5 Cycle 6 Cycle 7 Cycle 8
Inst0 Fetch Decode Execute Access M Store
Inst1 Fetch Decode Execute Access M Store
Inst2 Fetch Decode Execute Access M Store
Inst3 Fetch Decode Execute Access M Store
Inst4 Fetch Decode Execute Access M
Inst5 Fetch Decode Execute
Inst6 Fetch Decode
SOLUTION: Make separation between fetch and access memory

15. Solution Of Structural Hazard

16. IMPLEMENTATION OF STRUCTURAL
HAZARD

17. CONTROL HAZARD
 Control hazard, arising from the need to make a
decision based on the results of one instruction
while others are executing.
 Pipeline cannot operate normally due to non-
sequential control flow
 Common instances of structural hazards arise by
 Branch instruction(Unconditional OR Conditional) during execution time

18. CONTROL HAZARD

19. CONTROL HAZARD SOLUTION
SIMPLE TECHNIQUES TO HANDLE CONTROL
HAZARD
 For each branch, introduce a stall cycle
 Assume branch is not taken and start fetching the next instruction – if the
branch is taken , need hardware to cancel the effect of wrong path
instructions
 start fetch the next instruction (branch delay slot) and execute it anyway –
if the instruction turn out to be on the correct path, useful work was
done – if the instruction turns out to be on the wrong path, hopefully
program state is not lost

20. CONTROL HAZARD SOLUTION