The document explains the MIPS pipeline instruction-execution process that consists of five stages: fetch, decode, execute, memory access, and write back. It contrasts pipelined execution, which enhances performance and instruction throughput, with single-cycle execution. Additionally, it illustrates the operations on a data path and the advantage of pipelining in reducing execution time.

1. PIPELINED DATA PATH
MIPS Pipeline Instruction-execution classically takes 5 steps
1. Fetch
2. Decode
3. Execute
4. Memory Access
5. Write Back
Fetch Instruction from Memory
Decode the Instruction and Read Registers
Execute the operation / Calculate an address
Access an operand in Data Memory
Write the result into a register

2. The Simple Data Path

3. IF ID EX MEM WB
IF ID EX MEM WBInst 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK CYCLES
PROGRAMINSTRUCTIONS
Instruction 1 Instruction 1 Instruction 1 Instruction 1 Instruction 1
EXECUTION WITHOUT PIPELINING
SINGLE CYCLE IMPLEMENTATION

4. IF ID EX MEM WB
IF ID EX MEM WBInst 1
Inst 2 IF ID EX MEM WB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK CYCLES
PROGRAMINSTRUCTIONS
Instruction 2 Instruction 2 Instruction 2 Instruction 2 Instruction 2
EXECUTION WITHOUT PIPELINING
SINGLE CYCLE IMPLEMENTATION

5. IF ID EX MEM WB
IF ID EX MEM WBInst 1
Inst 2 IF ID EX MEM WB
Inst 3 IF ID EX MEM WB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK CYCLES
PROGRAMINSTRUCTIONS
Instruction 3 Instruction 3 Instruction 3 Instruction 3 Instruction 3
EXECUTION WITHOUT PIPELINING
SINGLE CYCLE IMPLEMENTATION

6. IF ID EX MEM WB
IF ID EX MEM WBlw $10,20($1)
IF ID EX MEM WB
IF ID EX MEM WB
1 2 3 4 5 6 7 8 9
CLOCK CYCLES
PROGRAMINSTRUCTIONS
Instruction 1 Instruction 1 Instruction 1 Instruction 1 Instruction 1
EXECUTION WITH PIPELINING
IF ID EX MEM WB
IF ID EX MEM WB
Instruction 2 Instruction 2Instruction 3 Instruction 2Instruction 3Instruction 4 Instruction 2Instruction 3Instruction 4Instruction 5
sub $11,$2,$3
add $12,$3,$4
lw $13,24($1)
add $14,$5,$6
Pipelining improves performance by increasing instruction throughput and
decreasing the execution time of an individual instruction

7. IMPLEMENTATION OF PIPELINING
A B C A B C
Ed: log |x.y|
A  x.y, B ||, C  log ()

8. Single Cycle Implementation of Data path

9. PIPELINED VERSION OF DATA PATH

10. INSTRUCTION FETCH

11. INSTRUCTION DECODE

12. EXECUTE

13. MEMORY ACCESS

14. WRITE BACK

15. IF ID EX MEM WB
IF ID EX MEM WBlw $10,20($1)
IF ID EX MEM WB
IF ID EX MEM WB
1 2 3 4 5 6 7 8 9
CLOCK CYCLES
PROGRAMINSTRUCTIONS
Instruction 1 Instruction 1 Instruction 1 Instruction 1 Instruction 1
EXECUTION WITH PIPELINING
IF ID EX MEM WB
IF ID EX MEM WB
Instruction 2 Instruction 2Instruction 3 Instruction 2Instruction 3Instruction 4 Instruction 2Instruction 3Instruction 4Instruction 5
sub $11,$2,$3
add $12,$3,$4
lw $13,24($1)
add $14,$5,$6

16. THE SINGLE-CLOCK-CYCLE DIAGRAM CORRESPONDING TO CLOCK CYCLE 5 OF THE PIPELINE