This document discusses digital VLSI design and power optimization. It covers several topics: - Sources of power consumption in CMOS circuits including static, short circuit, leakage, and dynamic power - Derivations of equations for short circuit and dynamic power - How to reduce power consumption by decreasing supply voltage, output swing, load capacitance, and switching activity - Sizing transistors for minimum power given a delay constraint - Graphical techniques for finding optimum voltage and frequency to minimize energy delay product

1. Digital VLSI Design
• Full Automation
• Maximum benefit of scaling
• High speed ,
• low power
• Robustness

2. Power dissipation

3. Why worry about power?
-- Heat Dissipation
DEC 21164
microprocessor power dissipation

4. Why worry about power — Portability
Multimedia Terminals
Laptop Computers
Digital Cellular Telephony
BATTERY
(40+ lbs)
Year
NominalCapacity(Watt-hours/lb)
Nickel-Cadium
Ni-Metal Hydride
65 70 75 80 85 90 95
0
10
20
30
40
50
Rechargable Lithium
Expected Battery Lifetime increase
over next 5 years: 30-40%

5. Where Does Power Go in CMOS?
• STATIC POWER---NIL
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors

6. Power consumption
• 4 components
Static power consumption
Short circuit power consumption
Leakage power consumption
Dynamic power consumption

7. • The total power in a CMOS circuit is given
by Ptotal = Pd + Psc + Ps where
 Pd is the dynamic average power (previous chart),
 Psc is the short circuit power,
 and Ps is the static power due to ratio circuit current,
junction leakage, and sub-threshold Ioff leakage current
• Short circuit current flows during the brief
transient when the pull down and pull up
devices both conduct at the same time
where one (or both) of the devices are in
saturation

8. Static power consumption

9. Short circuit power

10. CMOS Short-Circuit Power Dissipation
Derivation

11. Short Circuit Path

13. Modelling

14. t1- t2, Mos operates in saturation
At t2, current reaches its maximum value
At this point vin=vdd/2, because inverter is
symmetrical
I mean= 2x [2/T] x ∫Isat dt : Limits(t1, t2)
Conditions—Vin(t)=(Vdd/τ) t;
--assume vin increases linearly with time
tr = tf = trf
Psc = (/12) (Vdd – 2Vt)3 (trf/tpin)

15. • For a balanced CMOS inverter with
n=p= , and Vtn = |Vtp|, the short
circuit power can be expressed by
Psc = (/12)(Vdd – 2Vt)3 (tr/f/tpin)
where tpin is the period of the input
waveform and trf is the input rise time
(or fall time) tr = tf = trf

16. Effect of load cap on short circuit
power
• P short circuit reduces
• Reason---- output start switching after
input has completely stabilized

17. Effect of Cload

18. Dynamic energy consumption

19. Energy stored across capacitor

20. Dynamic power consumption-derivation

22. Average Dynamic Power in CMOS
Inverter
• Average dynamic power derivation:
– On negative going input, pull-up
device charges the load
capacitance. On positive going
input, pull-down device discharges
the load into ground.
– Average power given by
Pave = (1/T)CL (dvout/dt) (Vdd – vout)dt
+ (1/T)(-1) CL (dvout/dt) vout dt
where the first integral is taken from
0 to T/2 and the second integral is
from T/2 to T
• completion of the integral yields
Pave = CL Vdd
2 f where f = 1/T
• Note that the dynamic power is
independent of the typical device
parameters, but is simply a
function of power supply, load
capacitance and frequency of
the switching!

23. Vin Vout
CL
Energy/transition = CL * Vdd
2
Power = Energy/transition * f = CL * Vdd
2
* f
Need to reduce CL, Vdd, and f to reduce power.
Vdd
Not a function of transistor sizes!

24. Reduce power consumption
• Reduce Vdd
• Reduce swing at the output
• Reduce CL
• Reduce Switching activity
To keep same speed, can we reduce Vdd,
increase (w/L)?  No
Inc in W inc in CL

25. Dynamic Power Consumption - Revisited
Power = Energy/transition * transition rate
= CL * Vdd
2
* f01
= CL * Vdd
2 * P01* f
= CEFF * Vdd
2
* f
Power Dissipation is Data Dependent
Function of Switching Activity
CEFF = Effective Capacitance = CL * P01

27. Power Consumption is Data Dependent
uniform distribution of inputs
Example: Static 2 Input NOR Gate
Assume:
P(A=1) = 1/2
P(B=1) = 1/2
P(Out=1) = 1/4
P(01)
= 3/4  1/4 = 3/16
Then:
= P(Out=0).P(Out=1)
CEFF = 3/16 * CL

29. Transition Probabilities for Basic Gates
Non-uniform distribution of inputs

30. No feedback

31. Power consumption—Correlated signals
½1

34. Sizing for min. power
consumption
For a given delay constraint

35. Sizing for power consumption

37. Vdd=Vddref

38. Vdd=Vddref

39. Vdd≠ Vddref

41. Graphical solution

42. Why energy reduces for F increasing?
• Assume delay reqd is tpref=5ns.
• As F inc CL inc. delay (tp) inc. and dyn. energy inc.
linearly
• But as f inc delay reduces exponentially, energy inc.
• for F= 1 delay is already small and close to tpref). Inc in f
does not cause much reduction rather energy increment is
more
• For F large, delay and energy are large values
• Hence as f inc., delay reduces drastically (become less than
tpref ). Hence to have given delay= tpref, energy is dec.
which inc. delay to tpref.
• As f is increased further, delay reduction reduces, only
energy increases

43. Design example—0.25um technology, find f, Vdd for
tpref=0.2ns. Cext=10Cg1, γ=1, Vref=2.5v

44. Design a chain of inv for min delay, min energy

45. Power delay product
Indicates that energy required  0 for Vdd 0  erroneous

46. Energy delay product
Shd. Be minimum

47. Energy delay product
optimum Vdd