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COUNTERS
0 In electronics, counters can be implemented quite easily using
register-type circuits such as the flip-flop, and a wide variety of
classifications exist:
0 Asynchronous (ripple) counter – changing state bits are used as
clocks to subsequent state flip-flops
0 Synchronous counter – all state bits change under control of a single
clock
0 Decade counter – counts through ten states per stage
0 Up/down counter – counts both up and down, under command of a
control input
0 Ring counter – formed by a shift register with feedback connection in
a ring
0 Johnson counter – a twisted ring counter
COUNTERS
ASYNCHRONOUS/RIPPLE
COUNTERS
0 A THREE-bit asynchronous counter is shown below, where
only the first flip-flop is clocked by an external clock.
0 All subsequent flip-flops are clocked by the output of the
preceding flip-flop.
0 Asynchronous counters are also called ripple-counters because
of the way the clock pulse ripples it way through the flip-flops.
ASYNCHRONOUS/RIPPLE
COUNTERS
0 The MOD of the ripple counter or asynchronous counter is
2n where n flip-flops are used.
0 A counter may count up or count down or count up and down
depending on the input control.
0 If the uncomplemented output counts up, the complemented
output counts down.
0 There are many ways to implement the ripple counter
depending on the characteristics of the flip flops used and the
requirements of the count sequence.
0 Clock Trigger: Positive edged or Negative edged
0 JK or D flip-flops
0 Count Direction: Up, Down, or Up/Down
ASYNCHRONOUS/RIPPLE COUNTERS
Operation
0 The external clock is connected to the clock input of the first
flip-flop (FF0) only.
0 So, FF0 changes state at the falling edge of each clock pulse, but
FF1 changes only when triggered by the falling edge of the Q
output of FF0.
0 Because of the inherent propagation delay through a flip-flop,
the transition of the input clock pulse and a transition of the Q
output of FF0 can never occur at exactly the same time.
0 Therefore, the flip-flops cannot be triggered simultaneously,
producing an asynchronous operation.
ASYNCHRONOUS/RIPPLE COUNTERS
Operation
0 Note that for simplicity, the transitions of Q0, Q1, Q2 and CLK in
the timing diagram are shown.
ASYNCHRONOUS/RIPPLE COUNTERS
Operation
0 Asynchronous counter work like a ripple on water, hence also
named as Ripple Counter.
0 The 3-bit ripple counter circuit above has eight different states,
each one corresponding to a count value.
0 Similarly, a counter with n flip-flops can have 2n states.
0 The number of states in a counter is known as its mod (modulo)
number. Thus a 32-bit counter is a mod-8 counter.
ASYNCHRONOUS/RIPPLE COUNTERS
Truth Table
No. of Clock
Pulse
Binary Count Decimal Count
C B A
0 0 0 0 0
1 0 0 1 1
2 0 1 0 2
3 0 1 1 3
4 1 0 0 4
5 1 0 1 5
6 1 1 0 6
7 1 1 1 7
8 0 0 0 0
9 0 0 1 1
DECADE COUNTER
0 A decade counter is one that counts in decimal digits, rather
than binary.
0 A decade counter may have each digit binary encoded (BCD) or
other binary encodings.
0 A decade counter is a binary counter that is designed to count
to 10102 (decimal 10).
0 An ordinary four-stage counter can be easily modified to a
decade counter by adding a NAND gate as shown in figure
DECADE COUNTER
0 Notice that FF2 and FF4 provide the inputs to the NAND gate.
The NAND gate outputs are connected to the CLR input of each
of the FFs.
0 It counts from 0 to 9 and then resets to zero.
0 The counter output can be set to zero by pulsing the reset line
low.
0 The count then increments on each clock pulse until it reaches
1001 (decimal 9).
0 When it increments to 1010 (decimal 10) both inputs of the
NAND gate go high. The result is that the NAND output goes low,
and resets the counter to zero.
DECADE COUNTER
Truth Table
No. of
Clock Pulse
Binary Count Decimal Count
D C B A
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 1 0 1 0 10
DECADE COUNTER
ASSIGNMENT
Draw circuit diagram of MOD-12 Ripple Decade Counter with
truth table.
ASYNCHRONOUS UP/DOWN COUNTER
0 In certain applications a counter must be able to count both up
and down. The circuit below is a 3-bit up-down counter.
0 It counts up or down depending on the status of the control
signals UP and DOWN.
0 When the UP input is at 1 and the DOWN input is at 0, the NAND
network between FF0 and FF1 will gate the non-inverted output
(Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be
gated through the other NAND network into the clock input of
FF2. Thus the counter will count up.
ASYNCHRONOUS UP/DOWN COUNTER
0 When the control input UP is at 0 and DOWN is at 1, the
inverted outputs of FF0 and FF1 are gated into the clock inputs
of FF1 and FF2 respectively.
0 If the flip-flops are initially reset to 0's, then the counter will go
through the following sequence as input pulses are applied.
SYNCHRONOUS COUNTERS
0 In synchronous counters, the clock inputs of all the flip-flops are
connected together and are triggered by the input pulses. Thus,
all the flip-flops change state simultaneously (in parallel).
0 Circuit diagram below showing 2-bit synchronous counter.
0 The J and K inputs of FF0 are connected to HIGH.
0 FF1 has its J and K inputs connected to the output of FF0.
SYNCHRONOUS COUNTERS
0 The most important advantage of synchronous counters is that there is
no cumulative time delay because all flip-flops are triggered in
parallel.
0 Thus, the maximum operating frequency for this counter will be
significantly higher than for the corresponding ripple counter.
0 Frequency division is same at every stage.
3 Bit SYNCHRONOUS COUNTERS
0 In synchronous counters, the clock inputs of all the flip-flops are
connected together and are triggered by the input pulses.
0 Thus, all the flip-flops change state simultaneously (in parallel).
0 The circuit below is a 3-bit synchronous counter. The J and K inputs of
FF0 are connected to HIGH.
0 FF1 has its J and K inputs connected to the output of FF0, and the J and
K inputs of FF2 are connected to the output of an AND gate that is fed
by the outputs of FF0 and FF1.
3 Bit SYNCHRONOUS COUNTERS
Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0
and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to
change its state due to the AND gate.
• They are basically shift registers with the serial outputs
connected back to the serial inputs in order to produce
particular sequences.
• These registers are classified as counters because they
exhibit a specified sequence of states.
• Two of the most common types of shift register counters are
introduced here: the Ring counter and the Johnson counter.
SHIFT REGISTER COUNTERS
• A ring counter is basically a circulating shift register in
which the output of the most significant stage is fed back to
the input of the least significant stage.
• The following is a 4-bit ring counter constructed from D
flip-flops.
RING COUNTER
• The output of each stage is shifted into the next stage on the
positive edge of a clock pulse.
• If the CLEAR signal is high, all the flip flops except the first
one FF0 are reset to 0. FF0 is preset to 1 instead.
• Since the count sequence has 4 distinct states, the counter
can be considered as a mod-4 counter (or 4-bit counter).
• The major advantage of a ring counter over a binary counter
is that it is self-decoding.
• No extra decoding circuit is needed to determine what state
the counter is in.
RING COUNTER
RING COUNTER
4-bit ring counter
have 4 states so it
is Mod4, n-bits
counter can be
Mod-n
• Johnson counters are a variation of standard ring counters,
with the inverted output of the last stage fed back to the
input of the first stage.
• They are also known as twisted ring counters.
• An n-stage Johnson counter yields a count sequence of
length 2n, so it may be considered to be a mod-2n counter.
• The circuit below shows a 4-bit Johnson counter.
JOHNSON COUNTER
• The state sequence for the counter is given in the table .
JOHNSON COUNTER
JOHNSON COUNTER
7 SEGMENT DISPLAY
0 The common task of decoding from machine language
to decimal number is suggested in every digital
system.
0 The very common output device use to display
decimal numbers is Seven Segment Display.
0 The 7 segments of display are labeled (a through g) as
shown in figure.
7 SEGMENT DISPLAY
0 The each 7 segment display has 7 LED’s fabricated on
it.
0 The common 7 segment LED gives Reddish glow when
lit.
0 Figure show cut-view of 7 segment display.
7 SEGMENT DISPLAY
Seven Segment displays
can be classified in to two
types...
i) Common Anode
ii) Common Cathode
7 SEGMENT DISPLAY
7 SEGMENT DISPLAY
0 COMMON ANODE:-
0 In such type of display anode is made common and is
connected with +5V supply. The cathode of each LED is
connected with resistor as to avoid short circuit or high
current and is then connected with decoder which gives
low logic as an indication as shown in figure above.
0 COMMON CATHODE:-
0 In this type cathode is made common of all LED’s and
grounded. The anode is supplied with signal.

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Electronics Counters and Displays Guide

  • 1.
  • 2. COUNTERS 0 In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist: 0 Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops 0 Synchronous counter – all state bits change under control of a single clock 0 Decade counter – counts through ten states per stage 0 Up/down counter – counts both up and down, under command of a control input 0 Ring counter – formed by a shift register with feedback connection in a ring 0 Johnson counter – a twisted ring counter
  • 4. ASYNCHRONOUS/RIPPLE COUNTERS 0 A THREE-bit asynchronous counter is shown below, where only the first flip-flop is clocked by an external clock. 0 All subsequent flip-flops are clocked by the output of the preceding flip-flop. 0 Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
  • 5. ASYNCHRONOUS/RIPPLE COUNTERS 0 The MOD of the ripple counter or asynchronous counter is 2n where n flip-flops are used. 0 A counter may count up or count down or count up and down depending on the input control. 0 If the uncomplemented output counts up, the complemented output counts down. 0 There are many ways to implement the ripple counter depending on the characteristics of the flip flops used and the requirements of the count sequence. 0 Clock Trigger: Positive edged or Negative edged 0 JK or D flip-flops 0 Count Direction: Up, Down, or Up/Down
  • 6. ASYNCHRONOUS/RIPPLE COUNTERS Operation 0 The external clock is connected to the clock input of the first flip-flop (FF0) only. 0 So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0. 0 Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time. 0 Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation.
  • 7. ASYNCHRONOUS/RIPPLE COUNTERS Operation 0 Note that for simplicity, the transitions of Q0, Q1, Q2 and CLK in the timing diagram are shown.
  • 8. ASYNCHRONOUS/RIPPLE COUNTERS Operation 0 Asynchronous counter work like a ripple on water, hence also named as Ripple Counter. 0 The 3-bit ripple counter circuit above has eight different states, each one corresponding to a count value. 0 Similarly, a counter with n flip-flops can have 2n states. 0 The number of states in a counter is known as its mod (modulo) number. Thus a 32-bit counter is a mod-8 counter.
  • 9. ASYNCHRONOUS/RIPPLE COUNTERS Truth Table No. of Clock Pulse Binary Count Decimal Count C B A 0 0 0 0 0 1 0 0 1 1 2 0 1 0 2 3 0 1 1 3 4 1 0 0 4 5 1 0 1 5 6 1 1 0 6 7 1 1 1 7 8 0 0 0 0 9 0 0 1 1
  • 10. DECADE COUNTER 0 A decade counter is one that counts in decimal digits, rather than binary. 0 A decade counter may have each digit binary encoded (BCD) or other binary encodings. 0 A decade counter is a binary counter that is designed to count to 10102 (decimal 10). 0 An ordinary four-stage counter can be easily modified to a decade counter by adding a NAND gate as shown in figure
  • 11. DECADE COUNTER 0 Notice that FF2 and FF4 provide the inputs to the NAND gate. The NAND gate outputs are connected to the CLR input of each of the FFs. 0 It counts from 0 to 9 and then resets to zero. 0 The counter output can be set to zero by pulsing the reset line low. 0 The count then increments on each clock pulse until it reaches 1001 (decimal 9). 0 When it increments to 1010 (decimal 10) both inputs of the NAND gate go high. The result is that the NAND output goes low, and resets the counter to zero.
  • 12. DECADE COUNTER Truth Table No. of Clock Pulse Binary Count Decimal Count D C B A 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 2 3 0 0 1 1 3 4 0 1 0 0 4 5 0 1 0 1 5 6 0 1 1 0 6 7 0 1 1 1 7 8 1 0 0 0 8 9 1 0 0 1 9 10 1 0 1 0 10
  • 13. DECADE COUNTER ASSIGNMENT Draw circuit diagram of MOD-12 Ripple Decade Counter with truth table.
  • 14. ASYNCHRONOUS UP/DOWN COUNTER 0 In certain applications a counter must be able to count both up and down. The circuit below is a 3-bit up-down counter. 0 It counts up or down depending on the status of the control signals UP and DOWN. 0 When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter will count up.
  • 15. ASYNCHRONOUS UP/DOWN COUNTER 0 When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are gated into the clock inputs of FF1 and FF2 respectively. 0 If the flip-flops are initially reset to 0's, then the counter will go through the following sequence as input pulses are applied.
  • 16. SYNCHRONOUS COUNTERS 0 In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). 0 Circuit diagram below showing 2-bit synchronous counter. 0 The J and K inputs of FF0 are connected to HIGH. 0 FF1 has its J and K inputs connected to the output of FF0.
  • 17. SYNCHRONOUS COUNTERS 0 The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. 0 Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter. 0 Frequency division is same at every stage.
  • 18. 3 Bit SYNCHRONOUS COUNTERS 0 In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. 0 Thus, all the flip-flops change state simultaneously (in parallel). 0 The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. 0 FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.
  • 19. 3 Bit SYNCHRONOUS COUNTERS Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0 and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate.
  • 20. • They are basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. • These registers are classified as counters because they exhibit a specified sequence of states. • Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. SHIFT REGISTER COUNTERS
  • 21. • A ring counter is basically a circulating shift register in which the output of the most significant stage is fed back to the input of the least significant stage. • The following is a 4-bit ring counter constructed from D flip-flops. RING COUNTER
  • 22. • The output of each stage is shifted into the next stage on the positive edge of a clock pulse. • If the CLEAR signal is high, all the flip flops except the first one FF0 are reset to 0. FF0 is preset to 1 instead. • Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter (or 4-bit counter). • The major advantage of a ring counter over a binary counter is that it is self-decoding. • No extra decoding circuit is needed to determine what state the counter is in. RING COUNTER
  • 23. RING COUNTER 4-bit ring counter have 4 states so it is Mod4, n-bits counter can be Mod-n
  • 24. • Johnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the input of the first stage. • They are also known as twisted ring counters. • An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod-2n counter. • The circuit below shows a 4-bit Johnson counter. JOHNSON COUNTER
  • 25. • The state sequence for the counter is given in the table . JOHNSON COUNTER
  • 27. 7 SEGMENT DISPLAY 0 The common task of decoding from machine language to decimal number is suggested in every digital system. 0 The very common output device use to display decimal numbers is Seven Segment Display. 0 The 7 segments of display are labeled (a through g) as shown in figure.
  • 28. 7 SEGMENT DISPLAY 0 The each 7 segment display has 7 LED’s fabricated on it. 0 The common 7 segment LED gives Reddish glow when lit. 0 Figure show cut-view of 7 segment display.
  • 29. 7 SEGMENT DISPLAY Seven Segment displays can be classified in to two types... i) Common Anode ii) Common Cathode
  • 31. 7 SEGMENT DISPLAY 0 COMMON ANODE:- 0 In such type of display anode is made common and is connected with +5V supply. The cathode of each LED is connected with resistor as to avoid short circuit or high current and is then connected with decoder which gives low logic as an indication as shown in figure above. 0 COMMON CATHODE:- 0 In this type cathode is made common of all LED’s and grounded. The anode is supplied with signal.