Michael Chung has over 15 years of experience in physical design and chip integration. He has taped out over 20 large chips using Synopsys and Cadence tools. Currently he works at AMD implementing placement and routing for tiles from gate level input through timing optimization and signoff. Previously he worked at Volt implementing a north bridge block through the physical design flow.

1. Michael Chung
165 Heather Lane
Palo Alto, CA 94303
(650) 493-9228 (H)
(408) 666-7833 (C)
mchung60@hotmail.com
Objective: Physical Design and Integration area
Expertise: Strong experience in physical design and chip integration. Tape-out 20
large-scale chips by using various physical design tools.
Skills: Synopsis ICC Advance Place/Route tool, Cadence Advance Place/Route tool,
PrimeTime, Calibre, Apache power tool, Makefile, Perl, TCL, Verilog, and
Skill languages.
Experience:
Physical Design Contractor Volt s Inc. (2015)
• Physical design: Implement P/R Universal North bridge block from gate level input,
block floor plan, placement, CTS, placement optimization, timing optimization,
routing and ECO steps with TSMC 16nm technology.
- Successfully implemented cross bar congestion intense tiles by grouping and
region utilization strategy to resolve local congestion issues.
Physical Design Staff, Engineer AMD Inc. (2000 – present)
• Physical design: Created Place and Route flow and implement P/R from gate level
input, block floor plan, placement, CTS, placement optimization, timing optimization,
routing and ECO steps with TSMC 28nm/20nm technology.
- Successfully implemented the tiles including analog intense tiles with manually
hand editing.
- Successfully implemented cross bar congestion intense tiles by grouping and
region utilization strategy to resolve local congestion issues.
- Successfully implemented memory control tiles with complicated clock tree by
define and refine clocks tree to meet clock specification and finish P/R to boost
tile performance.
Top level switching fabric irregular tile Place/Route.
- Executed floorplanning, and created placement def to create semi-custom manual
placement, and output def to do physical awareness synthesis.
- Placed timing critical logics by group/region method and script placement.
- Executed scan chain re-order, stitch, and output def to back DFT team.
- Executed Clock Tree and Scan Clock Tree synthesis, and optimization.
- Executed Routing, and optimization to fix all the routing violation.
• Physical verification : Created and verification: Defined and executed chip
integration, verification flow from chip construction, and construction quality

2. checking, IP qualification, and layers checking, OD filling, Metal filling and
verification process
(DRC/LVS/Density/DFM/Antenna checking), IP checking to tape out ATI very
complex ATI graphical chip.
Successfully taped-out Tahiti, Hawaii, Fiji, and Xbox chip with over 6
billion stransistors counts with TSMC 28nm/20nm technology.
• Fullchip power verification: Performed full chip Apache power analysis
- Input files preparation: included customer block power model preparation, and
full chip timing window generation.
- Executed Apache soc full chip power analysis, and analysis results to provide
feedback to tiles owner.
• Physical Library management and development: Developed library management
program and library QA program to qualify library quality.
Included ports checking, cell names uniquification, delay table monotone, and
customer blocks drc/lvs qualifications.
• Created Makefile base automatic hard IP flow.
- Defined and setup RTL to gds flow from synthesis , floor plan, pin assignment, P/R
strategy and implemented the flow to get quality blocks.
• Interface CAD vendors and Foundry
- Worked with CAD vendor AE, and R&D engineer to improve Place/Route
performance, and DRC/LVS performance.
- Filled out foundry MT form, and worked with foundry inspecting mask , and
tape out database to make sure successfully tape out .
Physical CAD Engineer, Chameleon Inc. (1998-2000)
• Managed physical library by using Skill language.
• Performed physical library characterization, verification, and managements.
• CAD support, and maintain block Place/Route, integration, and physical verification flow.
Education:
• Master of Electrical Engineering, University of Utah, Salt Lake City
• Bachelor of Engineering Science, National Tsing-Hua University, Taiwan
Activity: Member of IEEE
Reference: Available upon request