1. Low power VLSI circuit design
Prepared by:
Dr. Vasudeva
Department of ECE
Malla Reddy Engineering College (A),
Hyderabad.
June 12, 2023
Dr. Vasudeva Deprtment of ECE, MREC (A) 1/37
2. Structure of the Chapter
Low-Voltage Low-Power Multipliers: Introduction
Overview of Multiplication
Types of Multiplier Architectures
▶ Vedic Multiplier
▶ Booth Multiplier
▶ Baugh- Wooley Multiplier
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3. Chapter IV
Introduction
Multipliers are fundamental arithmetic units used in digital systems
to perform the mathematical operation of multiplication. They are
essential components in various applications, including digital
signal processing (DSP), microprocessors, communication systems,
graphics processing units (GPUs), and many other computational
tasks.
Low-power multipliers are essential components in modern digital
systems, where power efficiency is a critical design consideration.
These multipliers are specifically designed to perform multiplication
operations while consuming minimal power, making them ideal for
battery-operated devices, portable electronics, and energy-efficient
systems.
The increasing demand for energy-efficient electronic devices, such
as smartphones, wearables, Internet of Things (IoT) devices, and
wireless sensor networks, has driven the need for low-power
multipliers.
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4. Chapter IV
Contd..
The primary function of a multiplier is to take two input values, often
referred to as operands or factors, and produce an output value called
the product. The product is the result of multiplying the two input values
together. Multipliers are capable of handling both integer and fractional
numbers, enabling precise numerical computations in digital systems.
Multipliers can be implemented using various architectures and
techniques, depending on the specific requirements of the application.
Some common multiplier architectures include:
Shift-and-Add Multiplication Shift-and-add multiplication is
similar to the multiplication performed by paper and pencil. This
method adds the multiplicand X to itself Y times, where Y denotes
the multiplier. To multiply two numbers by paper and pencil, the
algorithm is to take the digits of the multiplier one at a time from
right to left,
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5. Chapter IV
Contd..
multiplying the multiplicand by a single digit of the multiplier and
placing the intermediate product in the appropriate positions to the left
of the earlier results.
Array Multiplier: The array multiplier is a straightforward and
commonly used architecture. It utilizes an array of logic gates to
perform multiplication by implementing a series of partial product
terms and then summing them up to obtain the final product.
Booth Multiplier: The Booth multiplier is a hardware-efficient
architecture that reduces the number of partial product terms by
exploiting the redundancy in the input operands. It uses a coding
technique to represent the operands in signed-digit form, allowing
for more efficient multiplication with fewer partial products.
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6. Chapter IV
Contd..
Wallace Tree Multiplier: The Wallace tree multiplier is an
advanced architecture that reduces the number of partial product
terms and the overall complexity of the multiplier. It employs a
tree-like structure to accumulate partial products, resulting in a
more efficient and faster multiplication process.
Baugh-Wooley multiplier: It is based on the principle of three-term
addition and utilizes the properties of signed binary numbers to
simplify the multiplication process. It is specifically designed for
signed multiplication, where the operands are represented in two’s
complement form.
VEDIC Multiplier: Main algorithm of Vedic multiplication is
Urdhva Triyakbhyam. It is a general multiplication formula
applicable to all cases of multiplication. It literally means Vertically
and Crosswise and then adding all the results.
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7. Chapter IV
Unsigned Multiplication
Paper and Pencil Example:
Binary multiplication is easy
0 × multiplicand = 0
1 × multiplicand = multiplicand
Accomplished via shifting and addition
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8. Chapter IV
Multiplication Example
Consider: 11002 × 11012 , Product = 100111002
4-bit multiplicand and multiplier are used in this example
Multiplicand is zero extended because it is unsigned
0001
01100000
SLL Multiplicand and SRL Multiplier
00001100
Multiplier[0] = 0 => Do Nothing
0011
00110000
SLL Multiplicand and SRL Multiplier
00011000 0110
SLL Multiplicand and SRL Multiplier
0000
11000000
SLL Multiplicand and SRL Multiplier
00001100
Multiplier[0] = 1 => ADD +
00111100
Multiplier[0] = 1 => ADD +
10011100
Multiplier[0] = 1 => ADD +
2
00001100 00000000
1101
Initialize
0
1
3
4
Multiplicand Product
Multiplier
Iteration
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9. Chapter IV
Signed Multiplication
So far, we have dealt with unsigned integer multiplication
Convert multiplier and multiplicand into positive numbers
If negative then obtain the 2’s complement and remember the sign
Perform unsigned multiplication
Compute the sign of the product
If product sign < 0 then obtain the 2’s complement of the product
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10. Chapter IV
Signed Multiplication
� Case 1: Positive Multiplier
Multiplicand 11002 = -4
Multiplier × 01012 = +5
11111100
111100
Product 111011002 = -20
� Case 2: Negative Multiplier
Multiplicand 11002 = -4
Multiplier × 11012 = -3
11111100
111100
00100 (2's complement of 1100)
Product 000011002 = +12
Sign-extension
Sign-extension
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11. Chapter IV
Braun Multiplier
Consider two unsigned numbers X = Xn−1...X1XO & Y = Yn−1...Y1YO
The product P = P2n−1...P1PO, which results from multiplying the
multiplicand X by the multiplier Y, can be written in the following form
Braun’s array multiplier of n x n requires n(n - 1) adders and n2 AND
gates.
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12. Chapter IV
Braun Multiplier
Figure: Partial products of a 4 X 4 unsigned integer multiplication
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15. Chapter IV
Braun Multiplier
Figure: (b) AND cell; (c) AND with full-adder cell; (d) full-adder cell.
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16. Chapter IV
Baugh-Wooley Multiplier
It was noted that Braun multiplier performs multiplication of
unsigned numbers.
The Baugh-Wooley technique was developed to design regular direct
multipliers for two’s complement numbers. This direct approach
does not need any two’s complementing operations prior to
multiplication.
Let us consider two-numbers X and Y with the following form
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17. Chapter IV
Baugh-Wooley Multiplier
The product P = XY is given by the following equation
In order to avoid the use of subtractor cells and use only adders, the
negative terms should be transformed. So
Using this property, the product P becomes
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18. Chapter IV
Baugh-Wooley Multiplier
Using the above relation an n x n multiplier, using only adders, can
be implemented. The schematic circuit diagram of a 4 x 4 two’s
complement multiplier based on Baugh-Wooley’s algorithm is shown.
The different cells composing the array are also shown. In this
scheme n( n - 1) + 3 full-adders are required. So for the case of n = 4
the array needs 15 adders.
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21. Chapter IV
Vedic Multiplier
Vedic Mathematics is the ancient system of mathematics which has a
unique technique of calculations based on 16 Sutras
Sri Bharti Krishna Tirthaji discovered Vedic mathematical
algorithms which yields faster multiplication by generating partial
products and summation in a single iterative step.
This sutra can be used for multiplication of 2x2, 4x4 and up to NxN
and also lot of computation time.
The Urdhva Tiryagbhyam sutra means the multiplication will be
done in vertical and cross wise operation.
The 2 X 2 Vedic multiplier is multiplied in three steps.
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22. Chapter IV
Vedic Multiplier
Step1: The first LSB of the two binary numbers to be multiplied
vertically and these numbers are added with the previous carry, in
this case the previous carry is zero.In the output bits the LSB bit will
be taken as a result and the remaining bits are forwarded to the next
step.
Step2: In this step the two binary bits can be multiplied cross wise
and the produced results will be added to the previously generated
carry and again, in the output bits the LSB bit will be taken as the
result and the remaining bits are forwarded to the next step
Step3: In this step the MSB bits to be multiplied vertically and the
result of this is added to the previously generated carry and the
output is taken as the result.
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25. Chapter IV
The Modified Booth Multiplier
For operands equal or greater than 16-bits, the modified Booth
algorithm have been used in almost all the designed multipliers.
It is based on recoding the two’s complement operand (i.e.,
multiplier) in order to reduce the number of partial products to be
added. This makes the multiplier faster and uses less hardware
(area).
For example, the modified Radix-2 algorithm is based on
partitioning the multiplier into overlapping groups of 3-bits, and
each group is decoded to generate the correct partial product.
The recoding of Y, using the modified Booth algorithm, generates
another number with the following five signed digits, -2, -1, 0, +1, +2.
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26. Chapter IV
The Modified Booth Multiplier
So the bits of the multiplier are
partitioned into groups of
overlapped 3-bits, each group
permits generation of a certain
partial product.
The five possible multiples of
the multiplicand are relatively
easy to generate following the
explanation given in Table.
Figure: Partial product selection
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27. Chapter IV
The Modified Booth Multiplier
Let X = 10010101 and Y = 01101001. The recoded digits of Y are
01101001 -> +2 -1 -2 +1
The bits are grouped into 3-bit groups overlapped by one bit and a
bit with a value of zero is added on the right side of Y as Y-l. So the
multiplication of two 8-bit numbers generates only 4 partial
products.
The number is then reduced by half. The partial product in this
example is represented on 9 bits.
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30. Chapter IV
The Modified Booth Multiplier
The ADD cell which generates 0 or 1. The schematic circuit of this cell is
shown in Fig. Two implementations are possible: one using pass
transistors controlled by the five signals defining the recoded digit code,
and the other one is an AND2 gate of the two signals -1 x and - 2 x .
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31. Chapter IV
The Modified Booth Multiplier
The partial product MUX (PP-MUX) which generates the partial
product. Fig.(b) shows the schematic of PP-MUX using CPL type logic.
The feedback PMOS, PI in this figure or in the one of Fig.(a) are used to
restore the high level to eliminate any DC current. This implementation
permits fast operation and low-power operation.
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32. Chapter IV
The Modified Booth Multiplier
The PP-FA (PP-HA) cells. They merge the PP-MUX circuit and a
full-adder (half-adder), respectively. CPL-like adder can be utilized for
fast operation and low-power.
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33. Chapter IV
Multiplier’s Comparison
Operation:
▶ Vedic Multiplier: Vedic multiplication is based on ancient Indian
mathematics principles and utilizes a set of sutras (formulas) to
perform multiplication. It involves techniques such as Nikhilam
(multiplying and subtracting), Urdhva-Tiryagbhyam (vertically and
crosswise), and others.
▶ Baugh-Wooley Multiplier: The Baugh-Wooley algorithm is a
technique for signed multiplication that utilizes two’s complement
representation. It performs partial product generation using a
combination of AND, OR, and XOR gates.
▶ Booth Multiplier: The Booth multiplication algorithm is a more
modern approach that reduces the number of partial products by
employing a technique called radix-4 recoding. It uses a set of states
(-2, -1, 0, and 1) for each bit, simplifying the multiplication process.
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34. Chapter IV
Multiplier’s Comparison
Partial Product Generation:
▶ Vedic Multiplier: Vedic multipliers generate a full set of partial
products for each bit of the multiplier, resulting in higher hardware
complexity.
▶ Baugh-Wooley Multiplier: Baugh-Wooley multipliers generate
partial products using a combination of AND and XOR gates. It
utilizes a signed-digit representation, reducing the number of partial
products required.
▶ Booth Multiplier: Booth multipliers also reduce the number of
partial products by using radix-4 recoding. This technique generates
partial products only where necessary, reducing hardware complexity.
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35. Chapter IV
Multiplier’s Comparison
Hardware Complexity:
▶ Vedic Multiplier: Vedic multipliers tend to have higher hardware
complexity due to the generation of full partial products for each bit.
▶ Baugh-Wooley Multiplier: Baugh-Wooley multipliers have lower
hardware complexity compared to Vedic multipliers. They require
fewer partial products and use simple AND and XOR gates.
▶ Booth Multiplier: Booth multipliers have reduced hardware
complexity due to the radix-4 recoding technique, which decreases
the number of partial products. They require fewer logic gates and
circuits.
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36. Chapter IV
Multiplier’s Comparison
Performance:
▶ Vedic Multiplier: Vedic multipliers can be efficient for small
operand sizes but become less efficient as the operand size increases.
They may have slower performance due to the complexity of
generating full partial products.
▶ Baugh-Wooley Multiplier: Baugh-Wooley multipliers are commonly
used for signed multiplication. They offer improved performance
compared to Vedic multipliers for signed multiplication operations.
▶ Booth Multiplier: Booth multipliers are generally more efficient,
especially for larger operand sizes. The reduction in the number of
partial products improves the overall performance, making Booth
multipliers commonly used in modern processors.
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