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    Low power sram Low power sram Document Transcript

    • INTERNATIONAL JOURNAL OF ELECTRONICS AND International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 2, March – April, 2013, pp. 257-263 IJECET© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI) ©IAEMEwww.jifactor.com LOW POWER SRAM Sapna1, Prof. B. P. Singh2 1 (M. Tech. Student, Electronics and Communication Engineering, Mody Institute of Technology & Science, Lakhshmangarh (Sikar), India, 2 (H.O.D., Electronics and Communication Engineering, Mody Institute of Technology & Science, Lakhshmangarh (Sikar), India, ABSTRACT Over the years, power requirement reduction in VLSI circuits has undergone tremendous advancement. Low power device design is now a vital field of research on account of increasing demand of portable devices. Sub-threshold operation holds promise for ultra low energy operation in emerging applications. This paper proposes a low power Schmitt Trigger based SRAM cell. Experimental results reveal that proposed design has reduced power consumption and has temperature sustainability. The simulation work has been carried out on Tanner EDA tool at 45nm technology. Keywords: Power consumption, SRAM, Schmitt Trigger, Sub-threshold, Tanner EDA. 1. INTRODUCTION The ongoing demand for reduction in energy consumption has motivated the design of sub-threshold digital circuits, which were shown to be reliable even for complex systems and memories. [1]. Supply voltage scaling has significant impact on the overall power consumption [2]. Aggressive scaling of transistor dimensions with each technology generation has resulted in increased integration density and improved device performance. Increased integration density along with the increased leakage necessities ultra low power operation in the present power constrained design environment. The power requirement for battery operated devices such as cell phones and medical devices are even more stringent [3]. Supply voltage scaling has remained the major focus of low power design. This has resulted in circuits operating at a supply voltage lower than the threshold voltage of a transistor. 257
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Sub-threshold current of a MOSFET device occurs when the gate-to-source voltage (VGS)of a device is lower than its threshold voltage (Vt). The reason for a growing importance of sub-threshold conduction is that the supply voltage has been continually scaled down, both to reducethe dynamic average power consumption of integrated circuits (the power that is consumed whenthe transistor is switching from an on-state to an off-state, which depends on the square of thesupply voltage), and to keep electric fields inside small devices low, to maintain devicereliability. [4]. The amount of memory required in a particular system depends on the type of theapplication. The semiconductor memory is generally classified according to the types of datastorage and data access. The read/write memory is commonly called Random Access Memory(RAM) [5]. RAMs are classified into SRAM (Static RAM) and DRAM (Dynamic RAM).SRAM and DRAM hold data but in different ways. DRAM requires the data to be refreshedperiodically in order to retain the data. SRAM does not need to be refreshed as the transistorsinside would continue to hold the data as long as the power supply is not cut off. The additionalcircuitry and timing needed to introduce the refresh creates some complications that makeDRAM memory slower and less desirable than SRAM. In human terms, memory is anorganisms ability to store, retain, and recall information and experiences. Similarly memoryrefers to physical devices is used to store data on a temporary or permanent basis. Semiconductormemory is capable of storing large quantities of digital information that are essential to all digitalsystem. Read/Write (R/W) memory must permit the modification (writing) of data bits stored inthe memory array, as well as their retrieval (reading).2. EXISTING SRAM CELLS The memory cell is a fundamental element in the design of low power high densitySRAMs because a significant portion of the memory’s size is taken by the cell area. The memorychip array contains the memory cells in which the data bits are already stored or in which theyare about to be stored. SRAM utilizes a flip-flop mechanism, which uses static latches and theseoperate in a manner similar to the way in which memory cells work. The electrical feedbackensures that voltage levels are sustained so that the data may retain active indefinitely for as longas power supply continues [5].2.1. Existing 6T SRAM Cell The 6T memory cell implementation in its simplest form is shown in Fig. 1 [5]. The cellis made up of two access transistors (M5 and M6) and a latch formed by two cross coupledinverters (M1, M3 and M2, M4). The pass transistors which are connected to twocomplementary bit lines BL and BLB are controlled by the word line signal WL. They act astransmission gates providing the bidirectional access between the latch and the bit lines. Before the read operation, the voltages at both bit lines get precharged to an equalizedpotential. When this particular memory cell is selected by asserting signal either BL or BLB willbe discharged to the ground terminal via M5 and M6. As a result a small potential 258
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Figure 1: Schematic of existing 6T SRAM cellDifference appears at the bit lines. A sense amplifier detects this potential difference andamplifies it to a full swing signal at the bit lines. During the write operation, the data bit to bewritten gets transferred to BL whereas its complement gets transferred to BLB. When the cell isselected by WL, the access transistors will store the data bit in a latch formed by two crosscoupled inverters. During hold operation, access transistors are turned off and the two crosscoupled inverters holds the data as long as the power supply is applied.2.2. Existing 7T SRAM Cell The 7T SRAM cell uses a novel write mechanism. In this cell, as shown in Fig. 2, thefeedback between the two inverters is cut off during the write operation [6]. The writemechanism depends only on one of the two bit lines, which reduces the activity factor ofdischarging the bit line pair. Figure 2: Schematic of existing 7T SRAM cell 259
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME3. SCHMITT TRIGGER In the previously reported SRAM cell, the basic element for the data storage is a crosscoupled inverter pair. Extra transistors are added to decouple the read and write operations. Thecross coupled inverter pair of an SRAM cell operating at ultra low supply voltage consumes highpower. So to improve the inverter characteristics, Schmitt Trigger configuration is used.3.1. Existing Schmitt Trigger The existing Schmitt Trigger (ST) circuit consists of three pMOS devices P1, P2, P3 andthree nMOS devices N1, N2, N3 as shown in Fig. 3 [1]. ST circuit has two different high-to-low(Vୌ ) and low-to-high (V୐ ) transition threshold voltages. When the threshold voltage of theexisting ST circuit is high, input signal goes up to Vୈୈ from ground. In other words, outputsignal is pulled low as input signal exceeds Vୌ . Similarly, when the threshold voltage of theexisting ST circuit is low, input signal goes down to ground fromVୈୈ . In other words, outputsignal is pulled up as input signal is lower than V୐ [7]. Figure 3: Schematic of existing Schmitt Trigger3.2. Modified Schmitt Trigger The modified Schmitt Trigger consists of four transistors P1, P2, P3, and N1 unlike theexisting ST, shown in Fig. 4 [7]. Thus the area and the leakage current are reduced as thetransistors N2 and N3 are removed. 260
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Figure 4: Schematic of modified Schmitt Trigger4. PROPOSED 11T SRAM CELL For a stable SRAM cell operating at lower supply voltages, power consumption of thecell should be reduced. Therefore a Schmitt Trigger based 11T SRAM cell has been proposedhaving built in feedback mechanism for reduced power consumption. The proposed 11T SRAMcell requires no architectural change compared to the existing 7T cell architecture except that thecross coupled inverter pair is replaced by the proposed Schmitt Trigger pair as shown in Fig. 5.Transistors M1, M3, M5 and M7 form one ST inverter while transistors M2, M4, M6 and M8form another ST inverter. M9 and M10 are access transistors. Figure 5: Schematic of proposed 11T SRAM cell 261
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME5. SIMULATION AND ANALYSIS In low power applications area, average power consumption and delay introduced by thedevice are the main technological aspects to prefer a design over its other counterparts. Theexisting and the proposed SRAM cells have been simulated using Tanner EDA Tools version13.0. The cells are tested for power consumption, delay and power-delay product at varioustemperatures. While working in sub-threshold region the voltage value is taken below thethreshold value that is 0.40V at all temperatures. For fair comparison, the aspect ratio of alltransistors is taken to be 1. The circuits are compared at 45nm technology. 7.00E-09 Power Consumption (watt) 6.00E-09 5.00E-09 4.00E-09 Existing 6T cell 3.00E-09 Existing 7T cell 2.00E-09 Proposed 11T cell 1.00E-09 0.00E+00 25 35 45 55 65 75 Temperature (°C) Figure 6: Power consumption at various temperatures Power consumption of the proposed cell is remarkably reduced as compared to theexisting cells, shown in Fig. 6. Also the power consumption decreases with increase intemperature. The obtained results of delay are shown in Table I. It clearly shows that delay forthe proposed cell is less than the existing cells. Table I: Delay at Various Temperatures Temperature Delay (°C) Existing 6T Existing 7T Proposed 11T cell cell cell 25 9.8692e-9 9.8713e-9 9.8693e-9 35 9.8682e-9 9.8703e-9 9.8685e-9 45 9.8672e-9 9.8694e-9 9.8678e-9 55 9.8663e-9 9.8686e-9 9.8671e-9 65 9.8654e-9 9.8678e-9 9.8666e-9 75 9.8646e-9 9.8670e-9 9.8660e-9 262
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Table II: PDP at Various Temperatures Temperature PDP (°C) Existing 6T cell Existing 7T cell Proposed 11T cell 25 5.6565e-17 5.4519e-17 2.9605e-17 35 5.6256e-17 5.1785e-17 2.9512e-17 45 5.5433e-17 4.8765e-17 2.9376e-17 55 5.4726e-17 4.5689e-17 2.9152e-17 65 5.3871e-17 4.3316e-17 2.8766e-17 75 5.3564e-17 4.1002e-17 2.8280e-17 The quantitative approach showing the variations of the Power-Delay Product (PDP) at differenttemperatures is presented in Table II. It depicts that PDP for the proposed cell is much lower than existingcells. Thus the proposed 11T SRAM cell is preferable for low power devices.6. CONCLUSION As the need of low power consumption and improvement in efficiency in the digital systems isincreasing day by day, the demand of low voltage, low power SRAM is escalating. The proposed 11TSRAM cell is compared with the existing 6T and 7T SRAM cells in sub-threshold region. The reason fora growing importance of sub-threshold conduction is that the supply voltage has continually scaled down,to reduce the power consumption. The proposed cell consumes less power and has reduced delay ascompared to the existing cells. The tremendous decrease in power-delay product reported in the proposed11T SRAM cell during the simulation make it better than the existing 6T and 7T SRAM cells. Thus theproposed cell is better viable options for low power and high performance applications.REFERENCES[1] N. Lotze, and Y. Manoli, A 62 mV 0.13 µm CMOS standard-cell-based design technique usingSchmitt-trigger Logic, IEEE J. Solid State Circuits, 47(1), 2012, 47-60.[2] J. P. Kulkarni and K. Roy, Ultralow-voltage process-variation-tolerant Schmitt-trigger-basedSRAM design, IEEE Trans. Very Large Scale Integration (VLSI) Syst., 20(2), 2012, 319-332.[3] J. P. Kulkarni, K. Kim, and K. Roy, A 160 mV robust Schmitt trigger based subthreshold SRAM,IEEE J. Solid State Circuits, 42(10), 2007, 2303–2313.[4] H. Soeleman, K. Roy, and B. Paul, Robust sub-threshold logic for ultra-low power operation,IEEE Trans. Very Large Scale Integration (VLSI) Syst., 9(1), 2001, 90-99.[5] K. Roy and K.-S. Yeo, Low-voltage, low-power VLSI Subsystems (New Delhi: Tata McGraw-HillInternational, 2009).[6] R. Aly, M. Faisal, and A. Bayoumi, Novel 7T SRAM cell for low power cache design, Proc.IEEE SOC Conf., 2005, 171-174.[7] Sapna and B. P. Singh, Low power schmitt trigger in sub-threshold region, International Conf. onRecent Trends in Computing and Communication Engineering, Hamirpur, India, 2013.[8] S. S. Khot, P. W. Wani, M. S. Sutaone and S.K.Bhise, “A Low Power 2.5 V, 5-Bit, 555-Mhz FlashAdc In 0.25µ Digital CMOS”, International Journal of Computer Engineering & Technology (IJCET)Volume 3, Issue 2, pp. 533 - 542 ISSN 0976 – 6367(Print), ISSN 0976 – 6375(Online) Published byIAEME. 263