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Low power vlsi design

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Low power vlsi design

  1. 1. LOW POWER VLSI DESIGN Vinchip Systems (a Design and Verification Company) Chennai.
  2. 2. Introduction Due to integration of components increased the power comes in lime light It is much important that handheld devices must possess low power devices For better performance For long run time (Battery time)
  3. 3. Definition Power Dissipation:  The rate of energy which is taken from the source and converted into heat
  4. 4. Types of Power Dissipation Static power dissipation  Due to leakage current Dynamic Power dissipation  Due to switching activities of transistor
  5. 5. Low Power Strategies
  6. 6. Low Power Design Space Three parts that we can perform low power techniques to reduce power dissipation  Voltage  Physical Capacitance  Switching activity
  7. 7. Supply voltage reduction Voltage reduction offers an effective means of power reduction A factor of two reduction in supply voltage yields a factor of four decreases in power consumption But the performance is also getting reduced To avoid the above stated problem,  Threshold voltage should be scaled down
  8. 8. Physical Capacitance Dynamic power consumption depends linearly on the physical capacitance being switched So minimizing capacitance offers another technique to for minimizing power consumption The capacitor can be kept as small by..  Minimum logic  Smaller devices  Fewer and shorter wires
  9. 9. Switching Activity There are two components to switching activity :  which determines the average periodicity of data arrivals  E (sw) which determines how many transitions each arrival will generate Switching activity is reduced by  Selecting proper algorithms architecture optimization,  Proper choice of logic topology  Logic level optimization which results in less power
  10. 10. Low power techniques
  11. 11. Low power Techniques Clock Gating  To reducing dynamic power dissipation  works by taking the enable conditions attached to registers, and uses them to gate the clocks Power Gating  High Vt sleep transistors which cut off VDD from a circuit block when the block is not switching  Also known as MTCMOS - Multi-Threshold CMOS
  12. 12. Calculation of Switching Activity Input Pattern Dependence Logic Function Logic Style Circuit Structure
  13. 13. Power Minimization Techniques Reducing chip and package capacitance  Process development such as SOI with partially or fully depleted wells  Advanced interconnect substrates such as Multi-Chip Modules (MCM). Scaling the supply voltage  Very effective  But often requires process technologies Employing better design techniques  The investment to reduce power by design is relatively small Using power management strategies  Various static and dynamic power management techniques
  14. 14. CAD Methodologies and Techniques Low power VLSI design can be achieved at various levels of the design process System Design  inactive hardware modules may be automatically turned off to save power Behavioral Synthesis  The behavioral synthesis process consists of three steps:  Allocation  Assignment and scheduling  These steps determine how many instances of each resource are needed Logic Synthesis Physical Design
  15. 15. Conclusion Low power VLSI is needed  Increasing of handheld devices  Increasing of complex device structure  Long battery life  Long device life

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