Final year project presentation

1. Graphene Based Transistors For Digital And
Analog Application
- A Simulation Study
Vishal Anand Agam Gupta Abhishek
Anand 1204059 1204056
1204055
Project Supervisor: Dr. M. W. Akram

2. Contents:-
• Motivation
• Project Roadmap
• Introduction
• Basics of Graphene
• Structure of GFET
• Software Introduction
• Software Simulation
• Parametric Results
• Comparisons
• Conclusion

3. Project Roadmap

4. Motivation:-
• Gordon Moore suggested that the number of
transistors get doubled approximately every
two years.
• The devices have become smaller.
• The introduction of new channel material,
device performance can be optimized.
Ref:[1].www.intelcorporations.com

5. Beyond C-MOS
Ref[2]:- Roadmap for 22 nm and beyond H. Iwai * Frontierl Research Center, Tokyo
Institute of Technology, 4259-J2-68, Nagatsuta, Midori-ku, Yokohama 226-8502, Japan
Ref[3] :- Carbon Nanotubes and Graphene Nanoribbons: Potentials for Nanoscale
Electrical Interconnects .Caterina Soldano , Saikat Talapatra and Swastik Kar

6. So What’s The Way Out ???
TWO
OPTIONS
NEW
DEVICE
STRUCTURE
FinFET
NEW
CHANNEL
MATERIAL
GRAPHENE
NANO
RIBBON GRAPHENE SHEETFinFET
Ref:-[4] www.google.com

7. What Is Graphene ?
Thermodynamically stable graphene sheet was first
discovered in 2004 by Giem and Novoselov.
Graphene is a two –dimensional sheet of sp2 bonded
carbon atoms arranged ina honeycomb crystal
structure with two carbon atoms in each unit cell.
Ref:- [5]Fabrication and Characterization of Graphene Field Effect Transistors by Sam Vaziri

8. Graphite
Single-layer Graphene
Single-wall Carbon
Nanotub
Ref:- [6] K. S. Novoselov et al., “Electric Field Effect in Atomically
Thin Carbon Films,” Science, 306 (2004) 666.

9. Types of Graphene structures

10. Ref:-[13]Characterization of Graphene Field Effect Transistors by Sam Vaziri

11. GNR Width(nm)
The variation of bandgaps of Arm-chair GNRs with width(W)

12. How to fabricate GNR ?
We can divide the GNR fabrication in two different methods :
• Chemical method: It involves assembling the small molecules into GNRs.Many
groups have reported the chemical fabrication of GNRs with
small molecules.
• Physical methods :- By gradual unzipping of one wall of a carbon nanotube to form
a
nanoribbon

13. Ref[7]:-Representation of the gradual unzipping of one wall of a carbon nanotube to form a
nanoribbon (Kosynkin et al, 2009)

14. Graphene Electronic Properties :
• Semi-metal or zero-gap semiconductor
• Linear dispersion relation Optoelectronics
• Massless dirac fermions, v ~ c/300 Intrinsic carrier mobility
(suspended graphene in vacuum 2,00,000 cm2 V-1s-1
• Carrier mobility of graphene on SiO2 at room-temperature
10,000-
20,000 cm2 V-1s-1
• Maximum current density J > 108 A/cm2
• Velocity saturation vsat = 5 x 107 cm/s (10 x Si, 2 x GaAs)
Fig:-Dispersion relation of graphene in fist Brillouin zone
Ref:-[8] Fabrication and Characterization of Graphene Field Effect Transistors by Sam Vaziri

15. 1. Mechanical properties
• Young’s modulus: ~1.10 TPa (Si ~ 130 GPa)
• Elastically stretchable by 20%
• Strongest material known
• Flexible
2. Thermal conductivity
• ∼5000 W/m•K at room temperature
Diamond: ∼2000 W/m•K, 10 x higher than Cu, Al
3. Transparent (only 1 atom thin)
Transparent flexible conductive electrodes
4. High surface to volume ratio
5. Most important advantage of Graphene technology is that it is compatible with standard sillicon
technology
making it easy and cost effective to integrate with the existing CMOS fabrication plants.

16. Simulation Side
• Our simulation software=> NanoTCAD ViDES
• Our documentation software=>Origin8, Plot Digitizer
• OS required=>Linux
• Languages=>Python, C.
• Equations used=>Solution of Poisson & Schrodinger equations, NEGF(Non-
Equilibrium Green’s Function )
• Modules required=>Pylab, NumPy, SciPy.

17. Why device simulation???
They allow to:
• predict the device behaviour
• understand the physical mechanisms underlying
the device operation
• test the impact of device design parameters on the
device performance (device optimization)

18. Ref:-[9] User Manual of NanoTcad Vides.

19. Mathematics Involved
Newton Raphson Method of iteration Jacobian Method
Ref:-[10] Ryaben'kii, Victor S.; Tsynkov, Semyon V. (2006), A Theoretical Introduction to Numerical Analysis

20. Template of 2D Metal Field Effect Transistor.
Ref:-[11] User Manual of NanoTcad Vides.

23. Ref:-[12] ViDES Graphical User Interface
Fig. showing graph between Id-Vgs-Vds Fig.showing graph between id-T-Vds
Results Obtained:-

24. GNR FET OUTPUT MODEL : -

26. Caliberation
Turn-on characteristics at Vds=0.3VOutput characteristics at Vgs=0.6V
Blue:-By nanoTcadVides
Red:- By papers=Performance comparison of graphene nanoribbon FET and MOSFET by
Gianluca Fiori and Giuseppe Iannaccone.

27. Parameters:-
W=1.5 nm
L=14nm
Both gate sweep
Conclusion:-
As Vds is increased ,
current increases as it
is directly
proportional to Vds
and Vgs.

28. Parameters:-
W=1.5 nm
L=14nm
Both gate sweep
Conclusion:-
At particular value of Vds
as different Vgs are
applied, current increases
to a large extent.

29. Parameters:-
Vg1=1.0V=Vg2
L=14nm
Conclusion:-
• The width(W) of GNR is
inversely proportional to
its bandgap(eV).
• Therefore as W increases
bandgap decreases and
the device shows metallic
characteristics as the
device enters into
saturation at lower value
of Vds.

30. Parameters:-
W=1.5nm
Vg1=Vg2=1.0V
Conclusion:-
• Length(L) is inversely
proportional to the
drain current(Ids).
• Therefore as the length
is increased, the drain
current starts to
decrease.

31. Parameters:-
W=1.5nm
Vg1=Vg2=1.0
Both gate sweep
Conclusion:-
• Capacitance is inversely
prop. to oxide thickness.
• Ids is directly prop. to the
capacitance.
• Therefore as the oxide
thickness is increased, the
capacitance decreases and
the over all current
decreases.

32. Parameters:-
W=1.5nm
Vg1=1.0=Vg2(both gate sweep)
L=14nm
Conclusion:-
As the doping increases while
keeping the channel length
same, the increased no. of
carriers result in the increase
of particle-to-particle collision
and hence the mobility
decreases and the resultant
value of current is less.

33. Parameters:-
W=1.5nm
L=14nm
Vg1=Vg2=1.0(both gates
sweep)
Conclusion:-
• Capacitance of the device
is directly proportional to
the relative di-electric
constant.
• As the di-electric
constant increases,
capacitance increases
and hence the Ids value
increases.

34. Analog & Digital Parameters Calculation for GNRFETs
Graphs Used :
• Id vs Vgs for different Vds
• Id vs Vgs for different GNR width
• Id vs Vds for different Vgs
• Id vs Vds for different GNR width
Digital Parameters: Analog Parameters:
ION/IOFF ratio Trans-conductance (gm)
Subthreshold Swing (SS) Drain Resistance (rd)
DIBL (mV/V) Amplification factor (µ)

35. Digital Parameters
ION/IOFF ratio: It is the figure of merit for having high performance (more ION) and low leakage power (less
IOFF) for the CMOS transistors. Typically more gate control leads to more ION/IOFF ratio.
Subthreshold Swing (SS): The subthreshold swing is defined as the gate voltage required to change the
drain current by one order of magnitude, 1 decade. In the MOSFET, the
subthreshold swing is limited to (kT/q) ln10 or 60 mV/dec at room
temperature.
SS= ∆Vgs / ∆ (log10 Id
DIBL (mV/V): Drain-induced barrier lowering or DIBL is a Short channel effect in MOSFETs referring
originally to a reduction of threshold voltage of the transistor at higher drain voltages.

36. Analog Parameters
Trans-conductance (gm): It is very often denoted as a conductance, gm, with a
subscript, m, for mutual. Trans-conductance is
defined as
follows:
Drain Resistance (rd): It is given by rd = ∆ Vds / ∆ Id Ω
Amplification factor (µ): It is given by gm * rd

37. Digital Parameters Calculation
• For different values of Vds
ION/IOFF ratio= (1*10^-6) / (1*10^-10) =1*10^4
SS= ∆Vgs / ∆ (log10 Id) =60 mV/dec
Fig Id vs Vgs at Vds=0.6V

38. Id vs Vgs curve at Vds=0.6V Id vs Vgs curve at Vds=0.8V
ION/IOFF ratio= (6.5*10^-6) / (2*10^-8) =325
SS= ∆Vgs / ∆ (log10 Id) = 210 mV/dec
ION/IOFF ratio= (6.5*10^-6) / (2.8*10^-
8)=232
SS= ∆Vgs / ∆ (log10 Id) = 190 mV/dec

39. For different GNR width
Id vs Vgs curve for W=1.5nm Id vs Vgs curve for W=2nm
ION/IOFF ratio= (9*10^-6) / (7*10^-7) =13
SS= ∆Vgs / ∆ (log10 Id) =175 mV/dec
ION/IOFF ratio= (6.5*10^-6) / (3.8*10^-7) =17
SS= ∆Vgs / ∆ (log10 Id) = (0.4-0.3) / (3*10^-6-
8*10^-7) = 450

40. Id vs Vgs curve for DIBL calculation
Vth
DD (by red curve) = 0.18V
Vth
LOW (by black curve) = 0.3V
VDD = 1V
VD
Low = 0.05V
DIBL= - (0.18- 0.3) / (1-0.05) = 126 mV/V

41. Analog Parameters:
Id vs Vds for W=1.5nm Id vs Vds for W=2.0 nm
gm = ∆ Id / ∆ Vgs = (4*10^-6 – 2.2*10^-6)/(0.4-
0.3) = 18 * 10^-6 Ω-1
rd = ∆ Vds / ∆ Id = (0.7-0.5) / (4.8*10^-6 –
3.8*10^-6) = 200 *10^3 Ω
µ = gm * rd = (18 * 10^-6 ) * (200 *10^3) = 3.6
gm = ∆ Id / ∆ Vgs = (3*10^-6 – 0.8*10^-6)/(0.4-
0.3) = 22 * 10^-6 Ω-1
rd = ∆ Vds / ∆ Id = (0.3-0.1) / (2.5*10^-6 –
1.55*10^-6) = 210 *10^3 Ω
µ = gm * rd = (22 * 10^-6 ) * (210 *10^3) = 4.62

42. Vds (volts) Ion/Ioff ratio SS(mV/dec)
0.05 10000 60
0.6 325 210
0.8 232 190
DIGITAL PARAMETERS
For different Vds
For different GNR width
GNR Width(nm) Ion/Ioff ratio SS(mV/dec)
1.5 13 175
2.0 17 450

43. ANALOG PARAMETERS
For different GNR width
GNR Width(nm) gm (Ω-1) (*10-6) rd (Ω) (*103) µ
1.5 18 200 3.6
2.0 22 210 4.62

44. Conclusion :
A model for the graphene FET using NEGF written in GUI Nano TCAD ViDES has been reported. The top-
gated graphene FET has been simulated.Typical simulations is then successfully performed for various
parameters of the grapheme FET. The modeling results agree with the experimental data. The model is not only
able to accurately describe ID-VG, ID-VD characteristics of the graphene FET, but also affects of channel
materials, gate materials, size of graphene FET, Doping,Channel width ,Channel length and Dielectric material
on the characteristics.
POSITIVES:
• According to scaling theory, as noted previously, a thin channel region allows short-channel effects to be
suppressed and thus makes it feasible to scale MOSFETs to very short gate lengths.
• The two- dimensional nature of graphene means it offers us the thinnest possible channel, so graphene
MOSFETs should be more scalable than their competitors.
• High velocity is observed in case of GNR FET ,which results in fast switching of the device and it gives better
performance compared to silicon based or GaAs device.

45. CHALLENGES :
• CMOS logic requires both n-channel and p-channel FETs with well-controlled threshold voltages, and
graphene FETs with all these properties have not yet been reported.
• These devices had relatively thick back-gate oxides, so voltage swings of several volts were needed for
switching, which is significantly more than the swings of 1 V and less needed to switch Si CMOS device
• Nanoribbon graphene, which does have a bandgap and results in transistors that can be switched off, has
serious fabrication issues because of the small widths required and the presence of edge disorder
Note : The latest ITRS road- map strongly recommends intensified research into graphene and even
contains a research and development schedule for car- bon-based nanoelectronics2. The race is still open and
the pros- pects for graphene devices are at least as promising as those for alternative concepts.

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