Rev2 HPPS Project 2007

H igh P erformance P rocessors and S ystems PdM – UIC joint master 2007 Instructor: Prof. Donatella Sciuto HPPS @ PdM – March 2007

Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

D ynamic Re configurability A pplied to M ulti-FPGA S ystems

DReAMS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Multi-FPGA Partitioning Alessandro Panella [email_address]

Project Organization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Partitioning ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The algorithm (1) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

The algorithm (2) ,[object Object],[object Object],[object Object],[object Object],[object Object]

What’s next? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Chimera Multi-FPGAs Architecture Definition Matteo Murgida [email_address]

Project Organization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: results (1/2) ,[object Object],[object Object]

Second Phase: results (2/2) ,[object Object]

What’s next ... ,[object Object],[object Object]

P rocessing E lements RE configuration I n R econfigurable A rchitectures Alessio Montone [email_address]

Second Phase Goals ,[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: results - III ,[object Object],(on a Core 2 Duo @ 2.33 GHz) Target FPGA Processor #BRAM Blocks #BRAM columns involved marBram execution time (ms) Commands overhead (approx. %) Bitstream size (Kbytes) VP7 Microblaze 4 2 179 1.5 56 VP7 PPC-405 8 3 203 1.5 84 VP7 Microblaze 8 5 263 1.5 136 VP20 PPC-405 8 3 248 1.5 112 VP20 Microblaze 8 5 326 1.5 160 VP20 Microblaze 16 5 326 1.5 160

What’s next… ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

R econfiguration O riented Me trics Alessandro Meroni [email_address]

Second Phase Objectives ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Application Analysis ,[object Object]

Metrics Evaluation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Simulators Analysis

Next Phase... ,[object Object],[object Object],[object Object],[object Object]

RE configurable C ommunication I nfrastructure F or E mbedded-systems Simone Corbetta [email_address]

April 2007/May 2007: objectives ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

April 2007/May 2007 : work (1/3) ,[object Object],[object Object],[object Object],[object Object],[object Object],Table 1 : Area requirements of a single-master/single-slave Network-on-Chip

April 2007/May 2007 : work (2/3) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

April 2007/May 2007 : work (3/3) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

May 2007/June 2007: objectives ,[object Object],[object Object],[object Object],[object Object],[object Object]

O perating Sy stem support for R econf i gurable S oC

Development of an OS architecture-independent layer for dynamic reconfiguration Ivan Beretta [email_address]

Project Overview ,[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: Goals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: Results (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: Results (2 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

What’s next… ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Design FLow Antonio Piazzi [email_address]

Project Organization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: results Output files: system.vhd; inserted device wrapper, ngc project files System.vhd scomposition (ArchGen based) Output files: fix.vhd and top.vhd Comunication infrastructure generation (COMiC based) Output file: <file name>.nmc <file name >.xdl Collect information about comunication infrastructure from xdl file Output file: port.cfg Adding information to top.vhd Start related flow tool Generation of the UCF file

Second Phase: results ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],Second Phase: results Manual process Automated process Planning VHDL gen. UCF and Com. Inf. Gen. Bitstream gen. Merging phase Planning VHDL gen. UCF and Com. Inf. Gen. Bitstream gen. Merging phase

Polaris ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Effects of 2D Reconfiguration in a Reconfigurable System Massimo Morandi [email_address]

2 nd Phase Goals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Allocation manager ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Most relevant works ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Evaluation ,[object Object],[object Object],[object Object]

Next Phase ,[object Object],[object Object],[object Object],[object Object],[object Object]

Relocation for 2D Reconfigurable Systems Marco Novati [email_address]

Goals of 2 nd phase ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

CRC Calculation ,[object Object],[object Object],[object Object],[object Object],[object Object]

Synthesis results ,[object Object],[object Object],[object Object]

What’s next… ,[object Object],[object Object],[object Object],[object Object]

H igh L evel R econfiguration Marco Maggioni marco.maggioni @dresd.org

Project Organization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Clustered Graph Metric Circuit Representation Reconfigurable Clustered Graph Area Latency Rec. Time Power Isomorphic Target Architecture Database Gcc Frontend Partitioning Algorithm PandA Scheduling Algorithm

Second Phase: Coloring ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Second Phase: Coloring ,[object Object],[object Object],[object Object],[object Object],[object Object],Clustered Graph Latency Area Rec. Time Power Needed Usefull

Second Phase: GraphGen ,[object Object],[object Object],[object Object],[object Object],[object Object]

What’s next… ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Rev2 HPPS Project 2007

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Rev2 HPPS Project 2007