HPPS 2008 - Maesani Moro


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HPPS 2008 - Maesani Moro

  1. 1. ENHANCEMENTS PROPOSAL FOR AN AUTOMATED TEST-TUBES ANALYSIS SYSTEM High Performance Processors and Systems Project Presentation Andrea MAESANI Federico MORO Prof. Donatella SCIUTO Tutor: Prof. Marco Domenico SANTAMBROGIO June 19 th , 2008
  2. 2. Inpeco <ul><li>“ Inpeco is a leading player in the fast growing Clinical Laboratory Automation market and Life Sciences supply industry that specializes in the development, production, distribution and servicing of enabling solutions to improve the process and operations of the laboratory” </li></ul><ul><li>(source: www.inpeco.com) </li></ul>
  3. 3. Inpeco system – description and limits <ul><li>Typical problems of fully centralized systems: </li></ul><ul><ul><li>Difficoult to face errors in one of the nodes or, even more serious, in the central server </li></ul></ul><ul><ul><li>Update, adding and removing of nodes complicated to be managed </li></ul></ul>
  4. 4. Proposed Architecture Local DB NODE
  5. 5. Rationale <ul><li>Aim </li></ul><ul><ul><li>Improve system performance (aka maximize test-tubes throughput) </li></ul></ul><ul><ul><ul><li>Identify limits and drawbacks of Inpeco’s architecture </li></ul></ul></ul><ul><li>Contributions </li></ul><ul><ul><li>Propose a formal model for the network to: </li></ul></ul><ul><ul><ul><li>Improve the network performance </li></ul></ul></ul><ul><ul><ul><li>Define the requirements for: </li></ul></ul></ul><ul><ul><ul><ul><li>A runtime network controller </li></ul></ul></ul></ul><ul><ul><ul><ul><li>An offline network simultator to identify the best placement for each node </li></ul></ul></ul></ul><ul><ul><li>Design a novel architecture for the node to: </li></ul></ul><ul><ul><ul><li>Speedup the updates in the node description to achieve future constraints/needs </li></ul></ul></ul><ul><ul><ul><li>Ennance future updates in the functionalities provided by the node </li></ul></ul></ul><ul><ul><ul><li>Support complex distributed systems to spread the computation and to distribute the network control over all the nodes </li></ul></ul></ul>
  6. 6. What's next... <ul><li>Network analysis </li></ul><ul><ul><li>Problem description </li></ul></ul><ul><ul><li>New proposed system </li></ul></ul><ul><ul><li>Similar cases analysis </li></ul></ul><ul><ul><ul><li>Mass Customization Manufacturing </li></ul></ul></ul><ul><ul><ul><li>Job Shop Scheduling Problem </li></ul></ul></ul><ul><ul><ul><li>Communication Systems </li></ul></ul></ul><ul><ul><li>Proposed solution </li></ul></ul><ul><ul><ul><li>Topology Definition </li></ul></ul></ul><ul><ul><ul><li>Scheduling Algorithm </li></ul></ul></ul><ul><li>Node case-study </li></ul><ul><li>Concluding remarks </li></ul>
  7. 7. Network Description <ul><li>Set of test-tubes divided into classes </li></ul><ul><li>Set of nodes , characterized by the operation they can perform (possibly more nodes performing the same operation), connected in a certain topology </li></ul><ul><li>Each test-tubes class requires to the system a well defined set of operations </li></ul>
  8. 8. Similar Cases Analysis (1) <ul><li>Mass Customization Manufacturing </li></ul><ul><ul><li>Set of products </li></ul></ul><ul><ul><li>Each problem can be divided into fixed module </li></ul></ul><ul><li>[1] Flexible Manufacturing System for Mass Customization Manufacturing – Guixiu Qiao, Roberto Lu, Charles McLean </li></ul><ul><li>Job Shop Scheduling Problem </li></ul><ul><ul><li>Set of jobs divided into classes </li></ul></ul><ul><ul><li>Set of nodes , characterized by the operation they can perform (possibly more nodes performing the same operation), NOT connected in a certain topology </li></ul></ul><ul><ul><li>Each job class requires to the system a well defined set of operations </li></ul></ul><ul><li>[2] Introduction to Job Shop Scheduling Problem – Qianjun Xu – 2001 </li></ul><ul><li>[3] The Job Shop Scheduling Problem with setup times – Francis Sourd – 1998 </li></ul><ul><li>[4] Heuristic Methods for Solving Job Shop Scheduling Problems – A. Garrido, M.A. Salido, F. Barber, M.A. Lopez </li></ul><ul><li>[5] Algorithms for the Job Shop Scheduling Problem – a comparison of different methods – J. Kaschel, T. Teich, G. Kobernik, B. Meier </li></ul>
  9. 9. Similar Cases Analysis (2) <ul><li>Communication Systems </li></ul><ul><ul><li>Set of information unit divided into classes </li></ul></ul><ul><ul><li>Set of nodes , characterized by the operation they can perform (possibly more nodes performing the same operation), connected in a certain topology </li></ul></ul><ul><li>[6] An Overview of the JMT Queueing Network Simulator – M. Bertoli, G. Casale, G. Serazzi </li></ul><ul><li>[7] Java Modelling Tools: an Open Source Suite for Queueing Network Modelling and Workload Analysis - M. Bertoli, G. Casale, G. Serazzi - 2006 </li></ul>
  10. 10. Similar Cases Analysis (3) <ul><li>Mass Customization Manufacturing </li></ul><ul><ul><li>Aim: formalization </li></ul></ul><ul><li>Job Shop Scheduling Problem </li></ul><ul><ul><li>No fixed network layout => explosion of possible states! </li></ul></ul><ul><ul><li>Their main problem consists in pruning possible paths in order to obtain a faster search </li></ul></ul><ul><li>Communication Systems </li></ul><ul><ul><li>Need to send information from a certain point to another through a network => no need to pass through some defined nodes </li></ul></ul>
  11. 11. Proposed Solution (1) <ul><li>The topology of the network is defined offline basing: </li></ul><ul><li>on statistical data </li></ul><ul><li>on information collected during a training time </li></ul><ul><li>Online system performance analysis may then eventually suggest later updates </li></ul>TOPOLOGY DEFINITION
  12. 12. Proposed Solution (2) <ul><li>Define all possible paths from current node to final node (-> n paths) – main difference from JSS </li></ul><ul><li>Define which of these (n) satisfy the requirements of the current test-tube (-> m paths =< n) – main difference from communication systems </li></ul><ul><li>Define which of these (m) is the optimal path – to improve performances : </li></ul><ul><ul><li>Shortest time until next required operation in performed </li></ul></ul><ul><ul><li>Shortest time until the test-tube exits the system </li></ul></ul>SCHEDULING ALGORITHM
  13. 13. Proposed Solutions (3) <ul><li>How to define the time until the test-tube exits the system? </li></ul><ul><li>Where: </li></ul><ul><li> time to pass through the node </li></ul><ul><li> queue time </li></ul><ul><li> time to move from one node to another </li></ul>
  14. 14. Addictional Remarks <ul><li>The system descripted also garantees: </li></ul><ul><li>TOPOLOGY UPDATE : all the modules are aware of changes in the topology of the system; this way all the scheduling decisions taken from update on will base on the new topology </li></ul><ul><li>TRACKING and ERROR DETECTION : knowledge of topology and test-tube passage memorization permit to track the movements and eventually to identify the exact point where an error has occurred </li></ul>
  15. 15. What's next... <ul><li>Network analysis </li></ul><ul><li>Node case-study </li></ul><ul><ul><li>Actual node architecture </li></ul></ul><ul><ul><li>Node problems </li></ul></ul><ul><ul><li>Proposed solution </li></ul></ul><ul><ul><li>Demonstrative architecture </li></ul></ul><ul><ul><ul><li>Target devices </li></ul></ul></ul><ul><ul><ul><li>Linux over FPGA </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><li>Conclusion </li></ul>
  16. 16. Inpeco's system: Node Architecture
  17. 17. Inpeco's system: Node Problems (1) <ul><li>Single point of failure </li></ul><ul><ul><li>A central server controls all the nodes </li></ul></ul><ul><li>Development time and cost of nodes </li></ul><ul><ul><li>Actually based on ASIC </li></ul></ul><ul><ul><ul><li>Design </li></ul></ul></ul><ul><ul><ul><li>Simulation </li></ul></ul></ul><ul><ul><ul><li>Synthetize HW (external manufacturers)‏ </li></ul></ul></ul><ul><ul><ul><li>Test </li></ul></ul></ul>
  18. 18. Inpeco's system: Node Problems (2) <ul><li>Expansions and upgrades </li></ul><ul><ul><li>Module-based system </li></ul></ul><ul><ul><ul><li>limited number of add-ons </li></ul></ul></ul><ul><ul><li>ASIC </li></ul></ul><ul><ul><ul><li>hard to adapt </li></ul></ul></ul><ul><ul><li>Problem of standards </li></ul></ul><ul><li>Faults detection and recovery </li></ul><ul><ul><li>Faults </li></ul></ul><ul><ul><ul><li>Manual procedures to find faults </li></ul></ul></ul><ul><ul><ul><li>Very time-consuming -> entire plant stopped for tests </li></ul></ul></ul><ul><ul><li>On-site intervention needed </li></ul></ul>
  19. 19. Proposed Solution <ul><li>An FPGA based device can solve many of these problems </li></ul><ul><li>Single Point of failure </li></ul><ul><ul><li>Distributed System -> Linux on FPGA </li></ul></ul><ul><li>Easy upgrades / expansions </li></ul><ul><ul><li>Reconfiguration </li></ul></ul><ul><ul><li>Stackable Boards </li></ul></ul><ul><li>Reduce development time and cost </li></ul><ul><ul><li>FPGA design cycle </li></ul></ul><ul><li>Fault tolerance and fault detection </li></ul><ul><ul><li>TMR </li></ul></ul><ul><ul><li>Radiation hardened devices </li></ul></ul><ul><ul><li>Feedback of outputs </li></ul></ul>
  20. 20. Node generic architecture <ul><li>Basic functionalities to achieve </li></ul><ul><ul><li>Support for complex distributed systems </li></ul></ul><ul><ul><ul><li>Linux </li></ul></ul></ul><ul><ul><li>Network connection </li></ul></ul><ul><ul><ul><li>Ethernet </li></ul></ul></ul><ul><ul><li>Manipulation of local HW from remote </li></ul></ul><ul><ul><ul><li>Simple client-server software to switch LEDs on/off </li></ul></ul></ul><ul><ul><li>Internal reconfiguration </li></ul></ul><ul><ul><ul><li>DRESD ICAP controller </li></ul></ul></ul>
  21. 21. Target devices <ul><li>Avnet VP7 Evaluation Board </li></ul><ul><ul><li>PowerPC hard-processor ( PPC 405 @ 300 MHz )‏ </li></ul></ul><ul><ul><li>μCLinux (2.4 kernel) + ELDK </li></ul></ul><ul><ul><li>Excellent support from Avnet (drivers...)‏ </li></ul></ul><ul><li>XUP VP30 Development Board </li></ul><ul><ul><li>Xilinx soft-processor (Microblaze @ 100 MHz)‏ </li></ul></ul><ul><ul><li>PetaLinux (2.6 kernel) + Petalogix </li></ul></ul><ul><ul><li>Lacks of drivers -> only used petalinux drivers </li></ul></ul>
  22. 22. Linux 2.6: PetaLogix Toolchain 1. Synthetize HW -> Bitstream 3. Build Libraries for PetaLinux 4. Configure kernel and compile -> image.bin (filesystem+kernel) 5. Download the Bitstream and the software image 2. Manual setup Kernel autoconfiguration (petalinux-autoconfig)‏ Import in PetaLinux (petalinux-new-platform)‏
  23. 23. Results (Avnet) <ul><li>Completely functional architecture on Avnet board </li></ul><ul><ul><li>Httpd server </li></ul></ul><ul><ul><li>Sample client-server demonstrative software </li></ul></ul><ul><ul><ul><li>Works! </li></ul></ul></ul><ul><ul><li>Internal reconfiguration (smallbit)‏ </li></ul></ul><ul><ul><ul><li>Simply switches on/off LEDs </li></ul></ul></ul>
  24. 24. Results (XUP) <ul><li>Partially working node architecture (kernel 2.6)‏ </li></ul><ul><ul><li>Fully working Linux distribution on the board </li></ul></ul><ul><ul><li>Clock skew impact directly on Ethernet performances </li></ul></ul><ul><ul><ul><li>Partially works ( 10% packet loss on the network )‏ </li></ul></ul></ul><ul><ul><li>Internal reconfiguration </li></ul></ul><ul><ul><ul><li>Need Port the ICAP kernel module to 2.6 kernel </li></ul></ul></ul><ul><ul><li>Sample client-server demonstrative software </li></ul></ul><ul><ul><ul><li>Works! (sometimes does not -> remember the Ethernet problems)‏ </li></ul></ul></ul>
  25. 25. Results – area requirements Microblaze DDR Controller Ethernet EMAC controller OPB 2 PLB Bus UART Controller VP7 Device VP30 Device VP30 IP-Cores area occupation
  26. 26. Conclusions <ul><li>Inpeco has a starting point to decide if take into account FPGA devices for future development </li></ul><ul><ul><li>FPGA devices can help to solve some of their problems </li></ul></ul><ul><ul><li>The proposed network design guarantees an improvement in performances, is much more flexible and error tolerant </li></ul></ul><ul><ul><li>Advantages of reconfigurable hardware </li></ul></ul><ul><li>Demonstrative architecture </li></ul><ul><ul><li>Complete Operating system with network support on a FPGA device </li></ul></ul><ul><ul><li>Software can greatly reduce development effort </li></ul></ul><ul><ul><li>Create very complex systems using a relatively simple node </li></ul></ul>
  27. 27. Questions? <ul><li>Thank you! </li></ul>