DRESD In a Nutshell July07

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DRESD In a Nutshell July07

  1. 1. DRESD in a Nutshell D ynamic R econfigurability in E mbedded S ystem D esign DRESD @ PdM – July 2007
  2. 2. Outline <ul><li>MicroLAB </li></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Motivations </li></ul></ul><ul><ul><li>Basic Definition </li></ul></ul><ul><ul><li>Reconfiguration in everyday life </li></ul></ul><ul><ul><li>SoC </li></ul></ul><ul><ul><li>New frontiers </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>DRESD @ PdM </li></ul></ul><ul><ul><li>DRESD in the World </li></ul></ul><ul><ul><li>What you can do… </li></ul></ul><ul><li>DRESD – Main Pojects </li></ul>
  3. 3. What’s next… <ul><li>MicroLAB </li></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Motivations </li></ul></ul><ul><ul><li>Basic Definition </li></ul></ul><ul><ul><li>Reconfiguration in everyday life </li></ul></ul><ul><ul><li>SoC </li></ul></ul><ul><ul><li>New frontiers </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>DRESD @ PdM </li></ul></ul><ul><ul><li>DRESD in the World </li></ul></ul><ul><ul><li>What you can do… </li></ul></ul><ul><li>DRESD – Main Pojects </li></ul>
  4. 4. <ul><li>MicroLAB organization: </li></ul><ul><ul><li>Thesis works: 50-60 /year </li></ul></ul><ul><ul><li>Class Projects: 80-100 /year </li></ul></ul><ul><ul><li>PhD students: 8 </li></ul></ul><ul><ul><li>Researchers: 4 </li></ul></ul><ul><ul><li>Professors: 8 </li></ul></ul><ul><li>MicroLAB Workstations: </li></ul><ul><ul><li>Linux: 26 </li></ul></ul><ul><ul><li>Windows: 3 </li></ul></ul><ul><ul><li>Laptop (Linux/Win): 20 </li></ul></ul><ul><ul><li>SUN: 15 </li></ul></ul>MicroLAB
  5. 5. What’s next… <ul><li>MicroLAB </li></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Motivations </li></ul></ul><ul><ul><li>Basic Definition </li></ul></ul><ul><ul><li>Reconfiguration in everyday life </li></ul></ul><ul><ul><li>SoC </li></ul></ul><ul><ul><li>New frontiers </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>DRESD @ PdM </li></ul></ul><ul><ul><li>DRESD in the World </li></ul></ul><ul><ul><li>What you can do… </li></ul></ul><ul><li>DRESD – Main Pojects </li></ul>
  6. 6. Motivations <ul><li>Increasing need for behavioral flexibility in embedded systems design </li></ul><ul><ul><li>Support of new standards, e.g. in media processing </li></ul></ul><ul><ul><li>Addition of new features </li></ul></ul><ul><li>Applications too large to fit on the device all at once </li></ul><ul><li>Speedup the overall computation of the final system </li></ul><ul><li>However, we need a way to process a specification to make it suitable for reconfigurable implementation </li></ul>
  7. 7. Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. </li></ul><ul><li>Gerald Estrin, 1960 </li></ul>
  8. 8. Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Complete – Static) (Partial – Dynamic) (Partial – Static)
  9. 9. SoC Reconfiguration f i x Partial Total Embedded
  10. 10. Different Scenarios... Single Device Distributed System
  11. 11. New frontiers <ul><li>Architectures </li></ul><ul><ul><li>Quantum computing </li></ul></ul><ul><ul><li>Reconfigurable computing is not equal to Xilinx </li></ul></ul><ul><ul><li>Nanotechnologies </li></ul></ul><ul><li>Models and paradigms </li></ul><ul><ul><li>Is the turing machine enough? </li></ul></ul><ul><ul><li>RDL: Reconfiguration Description language </li></ul></ul><ul><li>Applications </li></ul><ul><ul><li>Start from real worls needs </li></ul></ul><ul><ul><li>Benchmarking... </li></ul></ul><ul><li>Knowledge about all these disciplines will help transform reconfigurable computing from an art to a science. </li></ul>
  12. 12. What’s next… <ul><li>MicroLAB </li></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Motivations </li></ul></ul><ul><ul><li>Basic Definition </li></ul></ul><ul><ul><li>Reconfiguration in everyday life </li></ul></ul><ul><ul><li>SoC </li></ul></ul><ul><ul><li>New frontiers </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>DRESD @ PdM </li></ul></ul><ul><ul><li>DRESD in the World </li></ul></ul><ul><ul><li>What you can do… </li></ul></ul><ul><li>DRESD – Main Pojects </li></ul><ul><li>Questions? </li></ul>
  13. 13. DRESD Philosophy <ul><li>Do or do not! There’s no try! </li></ul><ul><li>Master Yoda </li></ul><ul><li>I need to believe that something </li></ul><ul><li>extraordinary is possible! </li></ul><ul><li>Alicia Nash </li></ul>
  14. 14. DRESD @ PdM <ul><li>and many more… </li></ul>
  15. 15. DRESD in regular curricula @ PdM a.a. 06/07 <ul><li>Undergraduate classes </li></ul><ul><ul><li>Logic Synthesis (projects) </li></ul></ul><ul><li>Graduate classes </li></ul><ul><ul><li>SW Laboratory (projects) </li></ul></ul><ul><ul><li>Computer Architecture (projects) </li></ul></ul><ul><ul><li>High Performance Processors and Systems (projects and regular class) </li></ul></ul><ul><ul><li>Soft Computing (projects) </li></ul></ul><ul><ul><li>IA and Robotics Lab (projects) </li></ul></ul><ul><ul><li>Hardware Design Methodologies (projects) </li></ul></ul><ul><ul><li>Hardware and Software Design Methodologies (projects) </li></ul></ul><ul><ul><li>Embedded Systems (projects) </li></ul></ul>
  16. 16. Students Overview <ul><li>Undergraduate degree </li></ul><ul><ul><li>03/04: 7 - 04/05: 18 - 05/06: 33 </li></ul></ul><ul><ul><li>Total (06/07): 19 </li></ul></ul><ul><ul><ul><li>3° year: 19 </li></ul></ul></ul><ul><li>Master degree </li></ul><ul><ul><li>Total: 20 </li></ul></ul><ul><ul><ul><li>4° year: 14 </li></ul></ul></ul><ul><ul><ul><li>5° year: 6 </li></ul></ul></ul><ul><li>PhD involved in DRESD </li></ul><ul><ul><li>Minor </li></ul></ul><ul><ul><ul><li>2°year: 1 </li></ul></ul></ul><ul><ul><li>Major </li></ul></ul><ul><ul><ul><li>1°year: 1 </li></ul></ul></ul><ul><ul><ul><li>3° year: 1 </li></ul></ul></ul>
  17. 17. DRESD in the WORLD @ June ‘07 <ul><li>Europe </li></ul><ul><ul><li>Paderborn University and HNI </li></ul></ul><ul><ul><li>EPFL </li></ul></ul><ul><li>USA </li></ul><ul><ul><li>UIC </li></ul></ul><ul><ul><li>Northwestern </li></ul></ul><ul><li>Companies </li></ul><ul><ul><li>Synplicity </li></ul></ul><ul><ul><li>ImpulseC </li></ul></ul><ul><ul><li>Siemens </li></ul></ul>
  18. 18. What you can do… <ul><li>Meeting </li></ul><ul><ul><li>Regular meeting every two weeks </li></ul></ul><ul><ul><li>DRESD Beer </li></ul></ul><ul><ul><li>3D-DRESD: the DRESD official meeting, July/August </li></ul></ul><ul><li>Funding, materials (i.e., boards, tools), sponsorship </li></ul><ul><li>Web: www.dresd.org </li></ul><ul><li>Mailing List: [email_address] </li></ul>
  19. 19. What’s next… <ul><li>MicroLAB </li></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Motivations </li></ul></ul><ul><ul><li>Basic Definition </li></ul></ul><ul><ul><li>Reconfiguration in everyday life </li></ul></ul><ul><ul><li>SoC </li></ul></ul><ul><ul><li>New frontiers </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>DRESD @ PdM </li></ul></ul><ul><ul><li>DRESD in the World </li></ul></ul><ul><ul><li>What you can do… </li></ul></ul><ul><li>DRESD – Main Pojects </li></ul>
  20. 20. DRESD – Main Projects <ul><li>Blanket - architectures </li></ul><ul><li>Caronte – design flow </li></ul><ul><li>CITiES – communication infrastructure </li></ul><ul><li>DReAMS – multi-FPGAs </li></ul><ul><li>HLR – theoretical aspects </li></ul><ul><li>OSyRiS – operating system support </li></ul><ul><li>Polaris – placement and relocation </li></ul><ul><li>RDL - modeling and system specification </li></ul><ul><li>R4R - reliability </li></ul><ul><li>SyCERS – simulation </li></ul><ul><li>... Retargetable Compiler </li></ul><ul><li>... EHW – evolvable HW </li></ul>
  21. 21. Blanket <ul><li>YaRA - Y ara is not a nother R econfigurable A rchitecture </li></ul><ul><ul><li>Support relocation </li></ul></ul><ul><ul><li>Different communciation infrastructures </li></ul></ul><ul><ul><li>Hard/Soft-Core </li></ul></ul><ul><ul><li>Internal/External Reconfiguration </li></ul></ul><ul><li>HARPE </li></ul><ul><li>Harvard-based Processing </li></ul><ul><li>Element Tailored for Partial </li></ul><ul><li>Dynamic Reconfigurable </li></ul><ul><li>Architectures </li></ul>
  22. 22. Caronte
  23. 23. CITiES <ul><li>GOALS: </li></ul><ul><ul><li>Define a suitable approach ( methodology ) to the design of a complete communication-centric FPGA-based reconfigurable architecture </li></ul></ul><ul><ul><ul><li>Communication infrastructure design </li></ul></ul></ul><ul><ul><ul><li>Computational layer design </li></ul></ul></ul><ul><ul><ul><li>Metrics-driven design choices </li></ul></ul></ul><ul><li>MOTIVATIONS : </li></ul><ul><ul><li>Allow the implementation of application-adaptable reconfigurable architectures in order to achieve: </li></ul></ul><ul><ul><ul><li>Flexibility </li></ul></ul></ul><ul><ul><ul><li>Reliability </li></ul></ul></ul><ul><ul><ul><li>Performance </li></ul></ul></ul>
  24. 24. DReAMS <ul><li>Dynamic Reconfigurability </li></ul><ul><li>Applied to Multi-FPGA Systems </li></ul><ul><ul><li>Branch of DRESD project </li></ul></ul><ul><ul><li>Inherits architectures and tools </li></ul></ul><ul><li>Automatic workflow from VHDL system description to FPGA implementation </li></ul><ul><ul><li>VHDL parsing and system simulation </li></ul></ul><ul><ul><li>System creation over a specific architecture </li></ul></ul><ul><ul><li>Bitstream creation and download onto FPGAs </li></ul></ul>
  25. 25. HLR <ul><li>What is H igh L evel R econfiguration...? </li></ul><ul><ul><li>Theoretical approach to dynamic reconfiguration... </li></ul></ul><ul><li>Vision ... Reconfigurability has many advantages... </li></ul><ul><li>Mission ... Exploit these advantages to obtain best performance... </li></ul><ul><li>How ...? Adapting a system to this execution model managing complexity and drawbacks... </li></ul>
  26. 26. OSyRiS <ul><li>Provide software support for dynamic partial reconfiguration on Systems-on-Chip running an operating system (i.e., LINUX ) . </li></ul><ul><li>Issues: </li></ul><ul><ul><li>OS customization for specific architectures </li></ul></ul><ul><ul><li>Partial reconfiguration process management from the OS </li></ul></ul><ul><ul><li>Addition and removal of hardware reconfigurable components </li></ul></ul><ul><ul><li>Automatic loading and unloading of specific drivers for the IP-Cores upon components configuration/deconfiguration </li></ul></ul><ul><ul><li>Easier programming interface for specific drivers </li></ul></ul>
  27. 27. Polaris <ul><li>Create an integrated HW/SW system to manage relocation (1D and 2D) in reconfigurable architecture </li></ul><ul><ul><li>Maintain information on FPGA status </li></ul></ul><ul><ul><li>Decide of how to efficiently allocate tasks </li></ul></ul><ul><ul><li>Provide support for effective task allocation </li></ul></ul><ul><ul><li>Perform bitstream relocation </li></ul></ul>
  28. 28. RDL <ul><li>R econfiguration D esign L anguage </li></ul><ul><ul><li>Reconfiguration as an explicit feature in the system design </li></ul></ul><ul><ul><li>How to model a reconfigurable architecture </li></ul></ul><ul><ul><li>How to model/use reconfiguration at design-time </li></ul></ul><ul><ul><li>From DD (Desing Descriptio) to Bitstream </li></ul></ul>
  29. 29. R4R <ul><li>Designing reliable systems implemented on FPGAs, able to cope with the effects of faults caused by radiations </li></ul><ul><ul><li>Appling already known and well studied detection and recovery techniques to novel scenarios </li></ul></ul><ul><ul><li>Exploiting dynamic partial reconfiguration to trigger the reconfiguration of the affected portion of the architecture </li></ul></ul><ul><ul><ul><li>… while the rest of the system is still working </li></ul></ul></ul><ul><ul><ul><li>… without need to entirely reprogrammed the system </li></ul></ul></ul>
  30. 30. SyCERS <ul><li>Define a novel model to describe reconfigurable systems </li></ul><ul><ul><li>Based on know HDL (no new languages) </li></ul></ul><ul><ul><li>To be used in the early first stage of the project; to consider the reconfiguration at the system level </li></ul></ul><ul><li>Propose a complete framework for the simulation and the design of reconfigurable systems </li></ul><ul><ul><li>Providing system specification that can be simulated </li></ul></ul><ul><ul><li>Allowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time </li></ul></ul><ul><ul><li>Taking into account the software side of the final system </li></ul></ul>
  31. 31. END? <ul><li>Are you ready to see how deep the rabbit-hole goes?… </li></ul>

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