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Marco Santambrogio
Marco Santambrogio
Technology
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Operating System Support for Core Management in a Dynamic Reconfigurable Environment BY Ivan Beretta [email_address] Thesis committee: Shantanu Dutt (chair), Bhaskar DasGupta , Marco D. Santambrogio UIC Thesis Defense: May 7th, 2008
Rationale and Innovations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfigurable devices ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Some Definitions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Classification of reconfigurable architectures (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Classification of reconfigurable architectures (2 of 2) ,[object Object],[object Object],[object Object],[object Object]
Reconfiguration challenges ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Why do applications ask for IP-Cores? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Software applications and reconfiguration management ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Aims ,[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Related works ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Specific OSs for dynamic reconfiguration ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[1] Wigley and Kearney: The management of applications for reconfigurable computing using an operating system . In Seventh Asia-Pacific Computer Systems Architectures Conference (ACSAC2002), eds. F. Lai and J. Morris, Melbourne, Australia, 2002. ACS. [2] Wigley et al.: ReConfigME: a detailed implementation of an operating system for reconfigurable computing . Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International, April 2006. [3] Steiger et al.: Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks . Transactions on Computers, 53(11):1393–1407, November 2004.
Operating systems based on Linux ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[4] Donato et al.: Operating system support for dynamically reconfigurable SoC architectures . SOC Conference, 2005. Proceedings. IEEE International, pages 233–238, September 2005. [5] Williams and Bergmann: Embedded linux as a platform for dynamically self-reconfiguring systems-on-chip . In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ed. T. P. Plaks, pages 163–169. CSREA Press, June 2004. [6] So and Brodersen: Improving usability of FPGA-based reconfigurable computers through operating system support . Field Programmable Logic and Applications, 2006. FPL ’06. International Conference on, pages 1–6, 2006. [7] Donato, A., Ferrandi, F., Redaelli, M., Santambrogio, M. D., and Sciuto, D.: Exploiting partial dynamic reconfiguration for SOC design of complex application on FPGA platform . Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jorg Pfleiderer (Eds.): VLSI-SoC: From System To Sylicon, Springer 2007, pp.:87-109
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Caronte flow HW: Hardware RHW: Reconfigurable HW SW: Software
The software side of the Caronte flow ,[object Object],[object Object],[object Object],[object Object]
The software side of the Caronte flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfiguration Support ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IP-Core devices access ,[object Object],[object Object]
Implementation of reconfiguration support ,[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfigurable Process ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Centralized Manager ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
A further level of abstraction
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Implementation of the LRM
Selection of hardware/software implementations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Module caching ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Preemptive module allocation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Static Part IP-Core 1 IP-Core 2 IP-Core 3 IP-Core 4 Static Part IP-Core 2 IP-Core 3 IP-Core 1 Static Part IP-Core 2 IP-Core 3 IP-Core 1 IP-Core 4
Preemptive allocation rules ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Static Part IP-Core 1 IP-Core 2 IP-Core 3 IP-Core 4 Static Part IP-Core 1 IP-Core 2 IP-Core 3
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Validation Results ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Dynamic reconfiguration support (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Dynamic reconfiguration support (2 of 2) Throughput enhancement of ~ 2x compared to [7] [7] Donato, A., Ferrandi, F., Redaelli, M., Santambrogio, M. D., and Sciuto, D.: Exploiting partial dynamic reconfiguration for SOC design of complex application on FPGA platform . Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jorg Pfleiderer (Eds.): VLSI-SoC: From System To Sylicon, Springer 2007, pp.:87-109
First case study: simple logic application (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
First case study: simple logic application (2 of 2)
Second case study: cryptography application (1 of 2) ,[object Object],[object Object],[object Object],[object Object]
Second case study: cryptography application (2 of 2) ,[object Object],[object Object],AES IP-Core  DES IP-Core  Static part  Throughput w/ caching = 246 kB/s Throughput w/ caching = 436 kB/s
Evaluation of IP-Core preemption (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Evaluation of IP-Core preemption (2 of 2) [3] Steiger et al.: Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks . Transactions on Computers, 53(11):1393–1407, November 2004.
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concluding Remarks (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concluding Remarks (2 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Future works ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
References ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
General Information ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Questions ,[object Object]

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UIC Thesis Beretta

  • 1. Operating System Support for Core Management in a Dynamic Reconfigurable Environment BY Ivan Beretta [email_address] Thesis committee: Shantanu Dutt (chair), Bhaskar DasGupta , Marco D. Santambrogio UIC Thesis Defense: May 7th, 2008
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  • 19. The Caronte flow HW: Hardware RHW: Reconfigurable HW SW: Software
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  • 29. A further level of abstraction
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  • 39. Dynamic reconfiguration support (2 of 2) Throughput enhancement of ~ 2x compared to [7] [7] Donato, A., Ferrandi, F., Redaelli, M., Santambrogio, M. D., and Sciuto, D.: Exploiting partial dynamic reconfiguration for SOC design of complex application on FPGA platform . Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jorg Pfleiderer (Eds.): VLSI-SoC: From System To Sylicon, Springer 2007, pp.:87-109
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  • 41. First case study: simple logic application (2 of 2)
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  • 45. Evaluation of IP-Core preemption (2 of 2) [3] Steiger et al.: Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks . Transactions on Computers, 53(11):1393–1407, November 2004.
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