2. The ARM(ACRON RISC MACHINE) processor is a
Reduced Instruction Set Computer (RISC). The
RISC concept, originated in processor research
programs at Stanford and Berkeley universities
around 1980.
The ARM was originally developed at Acorn
Computers Limited of Cambridge, England, between
1983 and 1985. It was the first RISC
microprocessor developed for commercial use and
has some significant differences from subsequent
RISC architectures.
3. In 1990 ARM Limited was established as a separate
company specifically to widen the exploitation of
ARM technology, since when the ARM has been
licensed to many semiconductor manufacturers
around the world.
The ARM architecture incorporated a number of
features from the Berkeley RISC design, which
contains :
Pipelined Execution
Single-Cycle Execution
4. a load-store architecture
fixed-length 32-bit instructions
3-address instruction formats.
There are few features were rejected and it was made
suitable in newer version
ARM architecture can use Little endian or Big endian
format to access.
ARM architecture also supports 16-bit compressed
instruction set(Thumb Mode).
5. ARM Processor supports 6 data types :
8-bit signed and unsigned bytes
16-bit signed and unsigned Half-Words
32-bit signed and unsigned Words
ARM Instructions are all 32 bit Words.
6. The ARM has 7 basic operating Modes :
1) USER(unprivileged Mode under which most tasks
run)
2) FIQ(When an high priority interrupts is raised)
3) IRQ(When a low priority interrupts is raised)
4) SUPERVISOR
5) ABORT
6) Undefined
7) System
7. ARM has 37 Registers, all of which are 32-bits long.
1 dedicated Program Counter(PC)
1 dedicated Current Program Status Register(CPSR)
5 dedicated Saved Program Status Register(SPSR)
31 General Purpose Registers
8. Data Processing
Data Transfer
Block Transfer
Arithmetic operation
Logical Operation
Branching
Software Interrupt
9. Exceptions are usually used to handle unexpected
events which occurs during the execution of a program
such as interrupts or memory fault , also cover
software interrupts , undefined instruction traps and
the system reset.
Exceptions generated as the direct effect of executing
an instruction.
Exceptions generated as a side effect of instruction .
Exception generated externally.
10. When an exception arises , ARM completes the
current instruction and handle the exception which
starts from a specific memory location.
Exception entry and their vector addresses are listed in
table.
