ARM 7 and 9 Core Architecture Diagram

1. ARM
HISTORY
UK venture started in November 1990.
Established as Advanced RISC Machines Ltd.
Joint venture between Apple Computer, Acorn Computer Group, and VLSI Technology.
First product in 1991: the embedded RISC-based ARM6TM family.
INTRODUCTION
 ARM Holding plc. Holds Intellectual Property for RISC Processors and SoC (System on a Chip).
 The company does not manufacture its own chips, instead producing designs that its technology
partners can produce.
 Also produces a suite of development tools, as well as hardware and software products.
ARM CORE FAMILY
ARM7.
ARM9.
ARM9E.
ARM10E.
ARM11.
Cortex.
Xscale (ARM derivative by Intel).
All major chip manufacturers have licenses to one or several ARM cores
Analog Devices, Atmel, Cirrus, Fujitsu, IBM, Infineon, Intel, Mitsubishi, Motorola, National
Semiconductor, NEC, Philips, Sharp, ST Microelectronics, Texas Instruments, Toshiba
The most popular ARM core for the use in embedded systems is the ARM7TDMI

2. ARM 7
The family consists of the ARM7TDMI, ARM7TDMI-S and ARM7EJ-S processor cores and the ARM720T
cached processor macro cell.
ARM7TDMI:3 Stage Pipeline.
ARM710T:MMU (Memory mgmt unit)
ARM720T:8K unified cache.
DESIGN FOCUS
Power Efficient
Best performance for applications needs
RISC based
Capable of high volume with a short time to market
Investment in Advanced R&D which coincides with customers and partners
ARM7TDMI ARCHITECTURE:
32-bit RISC-processor core(32-bit instructions)
37 pieces of 32-bit integer registers (16 available)
3stage Pipelined
Von Neumann type bus structure (Harvard-ARM9 & above)
8/16/32 bit data types
7 modes of operation (usr,fiq,irq,svs,abt,sys,und)
Simple structure->reasonably good speed/power consumption ratio

3. BLOCK DIAGRAM ARM7
ARM7 has 37 registers all of which are 32-bit long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status register
30 general purpose registers

4. The current processor mode governs which of the several banks is accessible. Each mode can access
A particular set of r0-r12 registers
A particular r13 (Stack pointer, sp) and r14 (Link register, lr)
The program counter, r15 (pc)
The current program status register, cpsr
Privileged modes (except system) can also access a particular spsr (Saved Program Status Register)
The ARM has seven basic operating modes:
User: unprivileged mode under which most tasks run
FIQ: entered when a high priority (fast) interrupt is raised
IRQ: entered when a low priority (normal) interrupt is raised
Supervisor: entered on reset and when a Software Interrupt instruction is executed
Abort: used to handle memory access violations
Undef: used to handle undefined instructions
System: privileged mode using the same registers as user mode
Processor Operating States
From the point of view of the programmer, the ARM7 processor can be in one of the two states:
ARM State: This executes 32-bit, word aligned ARM instructions.
Thump State: This operates with 16-bit, halfword-aligned Thump instructions.
Switching Between Processor States
Entering Thump state:
Entering into Thump state can be achieved by executing a BX instruction with the state bit (bit 0)
set in the operand register.

5. Transition to Thump state also occurs automatically on return from an exception, for e.g; IRQ,
FIQ, UNDEF, ABORT, and SWI if the exception was entered with the processor in Thump state.
Entering ARM state
Entering into ARM state happens:
On execution of the BX instruction with the state bit clear in the operand register.
On the processor taking an exception, for e.g; IRQ,FIQ,RESET,UNDEF,ABORT,and SWI.
Memory Formats
The ARM processor views memory as a linear collection of bytes numbered upwards from zero, as
follows:
Bytes 0 to 3 Hold the 1st stored word
Bytes 4 to 7 Hold the 2nd stored word
and so on.
Words stored in memory as:
Big-endian format
Little-endian format
ARM9 Features
The ARM9TDMI core is a small, high performance, power-efficient 32-bit RISC processor. The core
features a five-stage pipeline, Harvard buses, Thumb extension and full debug access to all
programmer's model states. The Thumb code compression extension delivers 32-bit RISC performance
at 16-bit system costs through the efficient use of a second, compressed set of 16-bit instructions, which
reduces memory use by a third.
The ARM940T adds separate instruction and data caches to the two memory data buses for reduced
access time to both instructions and data. The ARM940T also contains a write buffer and a new
protection unit designed specifically for embedded operations. This new protection unit requires no

6. address translation and contains eight individually programmable instruction and data protection
regions. These can be specified as to base address, region size, and cache/buffer properties. During
debug, the ARM940T provides full debug access to the state of the protection unit registers and to the
contents of the caches.
In addition, the ARM940T is fully AMBA (Advanced Microcontroller Bus Architecture) compliant. AMBA
is a standard on-chip ASIC bus allowing rapid modular design of low power systems while simplifying
design reuse and test. ARM also provides a library of macrocell peripherals which conform to the AMBA
standard for easy ASIC development. By using AMBA with synthesized versions of the peripherals,
system hardware and software can be prototyped early in the design cycle, thereby reducing the risk of
design faults in the final system.
Both ARM9 products are supported by the ARM Software Development Toolkit version 2.11 (SDT2.11),
modeling and simulation support and a PID development board which implements AMBA.
Technical Details
ARM 9
ARM9TDMI includes 5-stage pipeline (fetch, decode, shifter/arithmetic logic unit (ALU), cache and
write-back), Thumb, Debug, Harvard buses.
ARM940T includes ARM9TDMI + 4KB instruction + 4KB data caches, write buffer, AMBA bus interface,
flexible memory protection unit, external coprocessor support.
Write buffer provides an 8 data word and 4 address capacity.
The protection unit consists of 8 variable size instruction regions, as well as 8 independent, variable
size data protection regions.
Predicted die size for the ARM9TDMI is 4mm2 based on 0.35-micron design rules and 3-layer metal.
Predicted die size for the ARM940T is 15mm2 based on 0.35-micron design rules and 3-layer metal.
Predicted clock frequency for both devices is approximately 150MHz, with a predicted MIPS rate of
165 @ 150MHz.
Power consumption for the ARM9TDMI is 1.5 mW of power per MHz at 2.5 volts.
Power consumption for the ARM940T is 4.5 mW of power per MHz at 3 volts.