ARM architecture, ARM different types of profile, AMBA Bus, Processor Modes, ARM Register sets

1. ARM Processor
- By Rathod Rajiv

2. 1. What is ARM ?
2. Support RISC Architecture
3. Load and Store Instruction Set
4. Low power consumption
5. Two control signal , memory read and memory write
6. Single clock cycle
7. Support Pipeline
8. Emphasis on Software
9. Fast Performance
10. More Instruction
11. Same address bus for I/O and Memory
12. Use for specific purpose application
ARM Basic
By Rathod Rajiv

3. By Rathod Rajiv
ARM Pipeline Execution

4. ARM Profile
1. Classic Processor
2. Cortex-M Series
3. Cortex-R Series
4. Cortex-A Series
By Rathod Rajiv

5. Classic Processor
1. ARM7
2. ARM9
3. ARM11
By Rathod Rajiv

6. Cortex-M Series
1. 32 bit
2. Optimized for microcontroller application
By Rathod Rajiv

7. Cortex-R Series
1. 32 bit
2. Provide very high performance and throughput with very
precise time.
3. Optimized for Real time System
4. Eg. Engine management system.
By Rathod Rajiv

8. Cortex-A Series
1. 32-bit and 64-bit
2. Supporting rich operating systems.
3. Use where application need platform Operating system.
Eg.Linux
By Rathod Rajiv

9. Classic & Embedded Processor
By Rathod Rajiv

10. Application Processor
By Rathod Rajiv

11. Inside ARM Based System
1. Within the device the component are connected together using
AMBA bus.
2. AMBA specifies two buses
1. High performance system bus AXI:
for connecting peripheral
2. Low power bus APB: for Memory Interface
By Rathod Rajiv

12. Processor Mode
1. Supervisor Mode
2. Fast Interrupt Request:
3. Interrupt Request
4. Abort
5. Undefined
6. System
7. User
By Rathod Rajiv

13. Supervisor Mode
1. Entered on reset and when supervisor call instruction is
executed
2. Supervisor mode is the mode that the processor is in after
reset and is generally the mode that an operating system
kernel operates in.
By Rathod Rajiv

14. Fast Interrupt Request Mode
1. Entered when high priority interrupt is raised
By Rathod Rajiv

15. Interrupt Request Mode
1. Entered when normal priority interrupt is raised
By Rathod Rajiv

16. Abort Mode
1. The processor enters abort mode when there is a failed
attempt to access memory
By Rathod Rajiv

17. Undefined Mode
1. Used to handle undefined instruction.
2. Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the
implementation.
By Rathod Rajiv

18. System Mode
1. System mode is a special version of user mode that allows full
read-write access to the cpsr.
By Rathod Rajiv

19. User Mode
1. User mode is used for programs and applications
By Rathod Rajiv

20. The ARM Register Set
1. Total 37 register
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
User mode
spsr
r13 (sp)
r14 (lr)
IRQ FIQ
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr spsr
r13 (sp)
r14 (lr)
Undef
spsr
r13 (sp)
r14 (lr)
Abort
spsr
r13 (sp)
r14 (lr)
SVC
Current mode Banked out registers
ARM has 37 registers, all 32-bits long
A subset of these registers is accessible in
each mode
Note: System mode uses the User mode
register set.
By Rathod Rajiv

21. Banked out register
1. Not in use register and not generally accessible
2. They coming to use when the processor change its mode
3. Eg. When you switch to IRQ mode , then the subset of the
registers change places and some of the IRQ registers coming
to the user mode
4. Each mode having its own stack space and and different
subset of register.
By Rathod Rajiv

22. Banked out register
5. SPSR is used for holding the snapshot of the current system
state at the moment the exception is taken, that is helpful to return
where we were very easy.
By Rathod Rajiv

23. Why FIQ handling is faster than handling
IRQ ?
By Rathod Rajiv

24.  Condition code flags
 N = Negative result from ALU
 Z = Zero result from ALU
 C = ALU operation carried out
 V = ALU operation overflowed
 Sticky Overflow flag - Q flag
 Indicates if saturation has occurred
 SIMD Condition code bits – GE[3:0]
 Used by some SIMD instructions
 IF THEN status bits – IT[abcde]
 Controls conditional execution of Thumb
instructions
 T bit
 T = 0: Processor in ARM state
 T = 1: Processor in Thumb state
 J bit
 J = 1: Processor in Jazelle state
 Mode bits
 Specify the processor mode
 Interrupt Disable bits
 I = 1: Disables IRQ
 F = 1: Disables FIQ
 E bit
 E = 0: Data load/store is little endian
 E = 1: Data load/store is big endian
 A bit
 A = 1: Disable imprecise data aborts
f s x c
2731 28 671623 15 5 4 024
J
10 8919
Q TI F modeN Z C V [de] E AGE[3:0]
Program Status Registers
By Rathod Rajiv

25. Thanks
By Rathod Rajiv