2. HISTORY
Previously known as Advanced RISC
Machine
ARM architecture is 32 – bit RISC processor
architecture
Developed by ARM Limited
Widely used in embedded systems
ARM 11 family compromises four series of
processors that implement the ARM
architecture v6
3. HISTORY
ARM 11 is the first implementation of the ARMv6
instruction set architecture
It is the base for all family of ARM 11 cores
The key objective in developing ARM 11
microarchitecture was to deliver high
performance and low power consumption
together with low price
ARM 11 has impact on wide variety of
applications in wireless, consumer, networking
and automotive segments
4. PERFORMANCE
Superior performance of ARM 11 cores is
possible because of ARMv6 architecture
ARMv6 delivers superior performance
trough:
1. Media processing extensions
2. Improved cache architecture
3. Improved exception and interrupt handling
4. Unaligned and mixed – endian data support
5. FEATURES
ARM 11 is Reduced Instruction Set
Computer (RISC) and it incorporates
following features:
1. Large uniform register file
2. Load/store architecture where data –
processing operations only operate on
register contents and not directly on
memory
3. Simple addressing modes with all load/store
addresses being determined from register
contents and instruction fields only
6. FEATURES
In addition ARM 11 architecture provides :
1. Control over ALU and the shifter in most
data processing instructions
2. Auto increment and auto decrement
addressing modes to optimize program
loops
3. Load and store multiple instructions to
maximize data throughput
4. Conditional execution on almost all
instructions to maximize execution
throughput
7. REGISTERS
ARM 11 has 31 general purpose 32-bit
registers and 6 status registers
At any of times only 16 of these registers are
visible and the others are used to speed up
exception processing.
3 of those 16 visible registers have special
roles (stack pointer, link register and program
counter).
8. EXCEPTIONS
ARM 11 supports 7 types of exceptions:
1. Reset
2. Attempted execution of undefined
instruction
3. Software interrupts instruction
4. Prefetch abort
5. Data abort
6. IRQ normal interrupt
7. FIQ fast interrupt
9. INSTRUCTION SET
ARM 11 instruction set can be divided in 6
classes of instructions:
1. Branch instructions
2. Data processing instructions
3. Status register transfer instructions
4. Load and store instructions
5. Coprocessors instructions
6. Exception generating instructions
10. ADDRESS SPACE
ARM 11 architecture uses a single flat
address space of 2³² bytes.
Byte addresses are treated as unsigned
numbers running from 0 to 2³² -1.
This address space is regarded as consisting
of 32-bits words each of whose address is
word aligned.
11. PIPELINE
To deliver enhanced performance keyword in
this architecture is pipeline
Pipeline in ARM 11 differs from all the
previous families of ARM cores in number of
stages it implements (8 stages)
It enable 40 % better output then all previous
cores
ARM 11 avoids delays in pipeline by using
forwarding and branch prediction
12. PIPELINE
These techniques provide great efficiency by
reducing pipeline stalls
ARM 11 microarchitecture pipeline is scalar
(issues one instruction at the time)
Improved memory access gives better overall
performance significantly in ARM 11
Instructions and data remain in caches longer
which in turn reduces cache misses
One of the major improvements in ARM 11
cores is non – blocking operation of memory
14. PARALLELISM
Even with pipeline that has single issue
instruction ARM 11 still manages to provide
parallelism
Parallelism is implemented at the back end of
pipeline where we have separate units for ALU
and separate units for LS (load and store)
To maximize parallel pipeline ARM 11 enables
out – of – order completion (instructions don’t
have dependencies on outcome of previous
instruction)
15. 64 - BIT
In some applications there is need for 64 – bit
processor
ARM 11 delivers 64 – bit structure without
actually implementing the 64 – bit solution
64 – bit data buses between processor integer
unit and instruction and data caches and also
between coprocessors and integer unit (64 – bit
path allows two instructions to be fetched from
cache in one cycle)
This gives great performance
16. SUPPORT FEATURES
ARM 11 supports floating point as design
option (cores with and cores without floating
point processing units)
ARM 11 supports :
1. Java Decode
2. V6 SIMD Instructions
3. MIA Instructions (as coprocessors)
4. Performance Range (350 MHz - > 1GHz)
17. APPLICATIONS
ARM 11 family of processors is widely used
in many areas
Some of the examples:
1. iPhone
2. iPod Touch
3. NVIDIA GoForce 6100
4. Nokia E71 smartphone
5. And many more…
18. REFERENCES
The ARM 11 Microarchitecture
David Cormie
April 2002
www.cs.uiuc.edu/class/fa05/cs433ug/PROCE
SSORS/ARM%2011%20MicroArchitecture
.pdf
www.arm.com (ARM 11 documentation)
www.wikipedia.org
