As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.

1. Content Addressable Memory Design in 3D pNML for
Energy-Aware Sustainable Computing¤
Nirupma Pathak†
Department of Computer Science and Engineering,
Maharishi University of
Information Technology, Lucknow, India
nirupmapathak@gmail.com
Bandan Kumar Bhoi
Department of Electronics & Telecommunication,
Veer Surendra Sai University of Technology, Burla, India
bkbhoi_etc@vssut.ac.in
Neeraj Kumar Misra†
Department of Electronics and Communication Engineering,
Bharat Institute of Engineering and Technology, Hyderabad, India
neeraj.mishra3@gmail.com
Santosh Kumar
Department of Computer Engineering and Information Technology
Swarrnim Startup & Innovation University Gandhinagar, Gujarat, India
sant7783@hotmail.com
Received 19 March 2020
Accepted 5 February 2022
Published 24 March 2022
As the semiconductor industry strives for downsizing and high speed, it is confronted with
increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML)
is an alternative approach to synthesize the digital logic circuits with high-density and low-
power consumption. We introduced an optimal design of content addressable memory (CAM)
memory based on perpendicular nano-magnetic logic (pNML). The main aim of this imple-
mentation is to synthesize CAM memory in terms of latency and other design parameters. The
implementation of the design is a multilayer approach, which is optimal. The synthesis ap-
proach and optimization are perfectly scalable across layout construction of designs. Here a new
logic gate in pNML technology is designed which is mainly used for matching of two input
numbers. According to insight, both memory unit and a matching unit in the pNML are
*This paper was recommended by Regional Editor Piero Malcovati.
†Corresponding authors.
Journal of Circuits, Systems, and Computers
Vol. 31, No. 10 (2022) 2250178 (14 pages)
#
.
c World Scienti¯c Publishing Company
DOI: 10.1142/S021812662250178X
2250178-1

2. introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed
pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
Keywords: Nanometer-scale; memory; nanomagnetic logic; information storage; nanoelectronics;
minority gate.
1. Introduction
Computing and memory elements are fundamental elements for all electronics
devices. Presently, CMOS technology is the backbone of these devices. However,
there are some limitations for the further shrinking of this technology due to leakage
current. Therefore, researchers are gathering toward alternative emerging technol-
ogy. Among them, perpendicular nanomagnetic logic (pNML) technology is most
promising due to the exciting features of nanomagnets.1
The features are that there is
no current °ow, unlike CMOS technology. Here logic values are transferred from one
magnet to another due to magnetic force,2,3
without physical current °ow this
technology has ultra-low power consumption. The second advantage of pNML is that
it is nonvolatile; therefore, it can store data at longtime. The third advantage is that
it can design logic circuits in three dimensions (3D) which is saving the area.
Therefore, its circuit density is improved compared to two-dimensional architectures.
Several digital circuits, such as Ex-OR gate, full adder, RAM memory are designed in
three-dimensional pNML technology.4–9
Here, we introduced a new layout of Con-
tent Addressable Memory (CAM) whose performance is superior to conventional
Random Access Memory (RAM). The Content Addressable Memory layout in
quantum-dot cellular automata (QCA) technology is available in the literature as
per Refs. 10 and 11. However, the demerit of QCA is that it is di±cult to fabricate
and for its operation, the cryogenic temperature is needed. So here, we designed the
CAM structure in pNML technology, which can operate in room temperature. For
layout design, we have used the MagCAD tool, which is introduced in Ref. 8.
In this paper, we have synthesized layout of the memory unit and matching the
logic design in pNML technology without changing the basic architecture of the
memory unit and matching the logic gate. The increasing demand for tiny nano-
electronics devices has a wide range of potential applications, and the demand for
new technologies-based circuits has developed in the ¯eld of nanotechnology as a
result. The CAM memory architecture unit is the searching of data with high speed.
Thus, this synthesis layout is optimal based on parameters' consideration such as
total area, critical delay and latency. Thus, the designs presented are cost-e®ective
based on parameters without changing CAM memory's fundamental structures
utilizing pNML technology. The pNML technique is used to fast the computing
process; the performance of the design is analyzed by setting the magnetic width
220 nm and grid size of 300 nm, whereas iNML utilizes 30 nm magnetic width, 50 nm
magnet height, magnet H distance 10 nm, magnet V distance 10 nm, number of clock
phases 3 and clock zone max series 4. According to the above drawing setting, pNML
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3. utilizes less magnet width and 3D approach for design synthesizing. In this paper, a
pNML-based CAM memory is synthesized for the ¯rst time, according to state-of-
the-art techniques. Area, critical delay and latency are a big impact in the circuit
synthesize; therefore, sometimes, circuit designer compromise for layout consider-
ation. However, in this suggested study, no parameters are sacri¯ced in order to
synthesize CAM memory circuits. For introducing a cost-e±cient CAM layout in
pNML, the study shows optimal parameters such as area and latency. The proposed
design of matching logic gates contains 5-minority gate and 6-inverter and memory
unit consists of 3-minority gate and 4-inverter. The constructed architecture of CAM
memory is optimized and can be used to miniaturization of the area in designing of
complex architecture such as microcontroller and processor. The proposed Content
memory addressing architecture supports the following:
. A model of CAM memory is proposed by using pNML technology.
. The bounded box area of CAM memory 3.556 m2 is evaluated.
. The cost e±ciency of the proposed CAM memory designs in NML is investigated.
. The estimate latency at di®erent input combinations for CAM memory is evaluated.
. Based on the minority voter gate, a multilayer layout of CAM memory is
synthesized with fast computation speed.
. The simulation results of CAM memory are veri¯ed and it is accurate like QCA
and CMOS-based design.
. Contrasting the novel CAM design with prior designs in consideration of para-
meters such as area and latency is investigated.
. The layout of CAM memory in pNML technology, which meets the requirement
of nanoelectronics con¯ne application, based on performance parameters and
physical existence, has been investigated.
This paper is structured as follows. In Sec. 2, the background of pNML is discussed.
In Sec. 3, proposed CAM architecture, layout in pNML technology is discussed. The
comparative analysis of the proposed CAM memory is discussed in Sec. 4 and ¯nally,
Sec. 5 concludes.
2. Technology pNML Basic Structure
One of the most promising technologies, nano-magnetic logic, has the potential to
replace CMOS technology. The inherent capacity of pNML technology to build 3D
logic circuits is an advantage. Magnets on neighboring planes are used to provide a
novel method of constructing digital logic circuits. NML is categorized into two
types, i.e., in-plane NML (iNML) and perpendicular NML (pNML) which is shown in
Figs. 1(a) and 1(b), respectively. In iNML, all magnets aligned in the same plane
but in pNML all magnets are perpendicular to each other. Therefore, in pNML,
three-dimensional circuit layout can be designed which is highly e±cient in circuit
Content Addressable Memory Design in 3D PNML
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4. density. According to magnetic direction orientations, magnets have logic 0 and logic 1
value, which is shown in Fig. 1. The basic element of the pNML is minority-voter gate,
which is illustrated in Fig. 2. The minority voter has A, B and C as three numbers of
inputs and Y as one output. Its pNML layout is detailed in Fig. 2(b). In this layout, the
magnet corresponding to input C is in the di®erent layer corresponding to other
magnets. Therefore, it has three-dimensional structures. Here the output value
depends upon minority values of the inputs. For example, if A ¼ 0, B ¼ 0 and C ¼ 1,
then output Y ¼ 1, which is the minority value of the inputs. In this technology, there
is no physical current °ow, which leads to minimal power consumptions. Here logic
values are transferred from inputs to output using magnetic force. The geometrical and
physical parameters used for simulation are mentioned in Table 1.
2.1. The proposed content addressable memory in pNML technology
CAM is one type of storage device, which operation principle is searching for data
with optimized speed. In this type of circuital memory, the time to obtain the
searching item is very less. This working prototype of CAM is not the same as RAM
model since every memory area in CAM is required to by its content. The proposed
CAM circuit has two numbers of components, one of which is memory unit and other
(a) (b)
Fig. 2. Minority gate: (a) block diagram and (b) 3D layout in pNML.
(a) (b)
Fig. 1. logic 0 and logic 1: (a) iNML and (b) pNML.
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5. is matching unit. For matching unit, we proposed a new logic gate in pNML, which
can improve the performance of CAM memory.
2.2. The proposed matching logic gate
The pNML architecture of the logic gate that performs the matching operation and
increases the CAM memory performance is shown here. The Boolean expression for
this gate is out ¼
K A F
ð Þ þ K. This gate has three numbers of inputs i.e., A, K and
F. Here F is the output of memory unit that is fed to it and K input acts as a switch
for the circuit. The principle of this gate is that if K ¼ 0, then the comparison of the
inputs A and F is done. Similarly, for K ¼ 1, input values A and F are any value or
named as do not care and output will be always 1. For example, if K ¼ 0, A ¼ 0 and
F ¼ 0, then in this case, A and F values will be compared. Here both are same, and then
the output will be 1. If K ¼ 0, A ¼ 0 and F ¼ 1, then output will be 0. Table 2 is the
truth table of match operation unit. The following are all of the modelling equations that
are addressed:
Y1 ¼ M1ðA; 1; FÞ ¼ AF;
Y2 ¼ M2ðF; 1; AÞ ¼ AF;
Y3 ¼ M3ðAF; 1; AFÞ ¼ AF þ AF ¼ A F þ AF ¼ A F;
Y4 ¼ M4ðK ; Y3; 0Þ;
Y4 ¼ K Y3 þ K þ Y3 ;
Y4 ¼ K þ Y3 ;
Y4 ¼ K Y3;
Y4 ¼ K ðA FÞ;
O ¼ M5ðK; 1; Y4Þ ¼ K :0 þ 0:Y4 þ Y4 K ¼ Y4 þ K ;
O ¼ Y4 þ K ¼ K ðA FÞ þ K:
Table 1. Default parameter of pNML technology used
in MagCAD 2.10.0 version.
Parameters Value
Nano wire width 40 nm
Size of grid 120 nm
Intermagnet space 150 nm
Co thickness (Co-Cobalt) 3.2 nm
Stack thickness 6.2 nm
Volume of ANC 1:68 1023 m3
Clock ¯led amplitude 560 Oe
Inverter coupling ¯eld strength 153 Oe
Minority gate coupling ¯eld strength 48 Oe
E®ective anisotropy 2:0 105 J/m3
Content Addressable Memory Design in 3D PNML
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6. Figures 3(a) and 3(b) show the logic gate and minority voter gate-based matching
design. In Fig. 3(c), the layout of the matching gate is shown. Its compilation result is
illustrated in Fig. 3(d). In this result, A, F and K are the inputs, whereas O is
the output.
2.3. The proposed memory unit
In memory unit, there are two numbers of inputs i.e., R/W and I. When the R/W ¼
0, the input value of I will be re°ected as output value F, as a consequence of the
write input. By providing R/W ¼ 1, the read operation is done. For example, if
Table 2. CAM match operation unit truth table.
K
Key register
bit
A
Argument
register bit
B
Bit received from
memory contents
O
Match register
output
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
(a)
(b)
Fig. 3. Matching logic gate: (a) logic diagram, (b) minority vote-based architecture, (c) pNML structure
and (d) simulation result.
N. Pathak et al.
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7. operation = write, I ¼ 1, R/W ¼ 0 and previous F = any value, then output F ¼ 1.
If operation ¼ write, I ¼ 1, R/W ¼ 0, previous F ¼ any value, then output F ¼ 0. If
operation ¼ read, I ¼ any value, R/W ¼ 1, then output F ¼ 1. Similarly, if
operation ¼ read, I ¼ any value, R/W ¼ 1, previous F ¼ 0, then output F ¼ 1.
Table 3 is the truth table of memory unit. The logic gate-based design of a memory
unit is shown in Fig. 4(a). Figure 4(b) shows the minority voter gate-based archi-
tecture of the memory unit. The pNML layout of the memory unit is detailed in
Table 3. CAM-memory unit truth table.
R/W I Previous F Output F Remarks
0 1 X 1 Write operation
0 0 X 0 Write operation
1 X 1 1 Read operation
1 X 0 0 Read operation
(c)
(d)
Fig. 3. (Continued)
Content Addressable Memory Design in 3D PNML
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8. (a)
(b)
(c)
Fig. 4. Memory unit design: (a) logic diagram, (b) minority vote-based architecture, (c) pNML structure
and (d) simulation result.
N. Pathak et al.
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9. Fig. 4(c) and its simulation result is shown in Fig. 4(d). All the modeling equations
related to proposed memory unit design are presented as follows:
F ¼ M3M1ðF; R=W; 0Þ; 1; M2ðR=W ; I; 0Þ;
F ¼ M3ð
F R=W þ
F þ R=W ; 1; R=W
I þ R=W þ
I Þ;
F ¼ M3ð
F þ R=W ; 1; R=W þ
I Þ;
F ¼ ðM3ðF R=W; 1; R=W IÞÞ;
F ¼ ðF R=WÞ þ ððR=W Þ IÞ:
2.4. The proposed content address memory structure
Content address memory (CAM) is a particular storage or memory type based on a
lookup table. The one-clock cycle here is adequate for the whole content of data
search. This allows us to seek the necessary data immediately and the memory gives
a matching signal. Figure 5(a) shows the block diagram of CAM design; this design
utilizes two blocks: one is memory unit and other one is matching logic unit. The
layout of Fig. 5(a) is presented in Fig. 5(c). The minority gate-based design of CAM
memory is presented in Fig. 5(b). Figure 5(c) presents the design of CAM memory in
pNML when grid size of 300 nm and magnet width of 220 nm. The performance
parameters are also analyzed based on the synthesis tool MagCAD and it is observed
the delay is lower as compared to QCA technology. Here the total circuit comprises a
memory unit and a matching unit, which is designed by using the minority voter gate
(Fig. 5(b)). The output of the memory unit is given as an input to the matching unit.
The pNML layout and simulation result are detailed in Fig. 5(c). The right half of
the pNML arrangement is the matching unit, with A and K as inputs, while the left
half-section is the memory unit, with I and R/W as inputs. The memory unit's
output is linked to the corresponding unit's input, and O is the ¯nal output, as shown
in Fig. 5(a).
(d)
Fig. 4. (Continued)
Content Addressable Memory Design in 3D PNML
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10. The performance analysis is detailed in Table 4. In this table, ¯ve cases of input
values are considered. If K ¼ 0, there are four types of latency; the minimum latency
is 3.91 E6 s. If K ¼ 1, the latency is 3.95 E6 s.
3. Comparative Result Analysis
The suggested CAM memory is compared against many existing literature papers, as
described in this part, to ensure that it is cost-e®ective. Table 5 shows a comparison
of the newly developed CAM memory with certain existing literature articles. In
comparison as per Refs. 11–20, our design uses optimal parameters in terms of delay.
As evidence from the comparison results presented in Table 5, proposed designs yield
better parameters such as area and latency as compared to another layout in dif-
ferent technologies such as CMOS and QCA. Layout analysis of the novel CAM
memory is veri¯ed by MAGCAD tool.
The majority of research papers accessible in state-of-the-the-art work do not
include robust design, fast computing, and do not operate the device at room tem-
perature. In terms of fast computing, area and operation at room temperature, this
propensity to apply current designs is ine±cient. The suggested CAM memory ar-
chitecture, however, improves latency. The area of the proposed design of CAM
memory is optimized, and the other parameters of design are also studied and ana-
lyzed by setting the magnetic width of 220 nm and grid size of 300 nm in MagCAD
tool using pNML technology. The comparison results show the dominance of the
novel CAM memory on the available reported designs in the literature. The proposed
(a)
(b)
Fig. 5. The proposed CAM structure: (a) logic diagram, (b) minority vote-based architecture, (c) pNML
layout and (d) simulation result.
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11. (c)
(d)
Fig. 5. (Continued)
Content Addressable Memory Design in 3D PNML
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12. layout is cost-e±cient, which can be considered as the base of architecture for
planning complex processor. The pitfall of these conventional technologies method
such as QCA and CMOS is that they are utilized more delay. QCA devices are not
operated at room temperature. Based on the literature review, QCA device is di±cult
the device work on room temperature. The proposed CAM architecture, which makes
use of nonmagnetic logic, computes quickly and can be implemented e®ectively at
room temperature, which is advantageous.
Table 4. Performance analysis of the proposed CAM
layout.
3D content addressable memory unit
Total area ¼ 3:556 m2
Critical path delay ¼ 1:679 E7s
Inputs Output Latency (s)
K RW I A O
0 0 0 0 1 3.91 E6
0 0 1 0 0 4.16 E6
0 0 0 1 0 3.91 E6
0 0 1 1 1 3.91 E6
1 X X X 1 3.95 E6
Table 5. Comparison of the proposed CAM design and existing QCA, and
CMOS technologies.
Design technologies Bounded box area
Clock cycle delay
(latency) Technologies
Ref. 11 0.14 m2 — QCA based
Ref. 12 17.54 m2 3 ns CMOS level
Ref. 13 17.46 m2 2.7 ns CMOS level
Ref. 14 232.2 mm2 — CMOS level
Ref. 15 1.73 mm2 — CMOS level
Ref. 16 0.53 mm2 — CMOS level
Ref. 17 0.14 m2 2 QCA based
Ref. 18 0.16 m2 2 QCA based
Ref. 19 0.13 m2 1.75 s QCA based
Ref. 20 0.08 m2 1.5 s QCA based
Ref. 21 0.14 m2 2 s QCA based
Ref. 22 0.11 m2 2 s QCA based
Ref. 23 0.11 m2 2 s QCA based
Ref. 24 0.13 m2 1.75 s QCA based
Ref. 25 0.08 m2 1.5 s QCA based
Ref. 25 0.16 m2 2 s QCA based
Proposed 3.556 m2 16.79 s pNML based
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13. 4. Conclusion
This work proposes a memory unit and match logic gate layout in pNML.
The synthesized content-addressing memory in pNML is cost-e®ective, taking into
account total area, critical path delay and latency. To make the CAM memory
design more robust, minimal latency and area, implementation of the proposed
circuit is chosen with nanomagnetic technology with multilayer pNML method,
which supports great bene¯t in synthesizing robust model of CAM memory. The
total area used by the circuit is 3.556 m2 and critical path delay is 16.79 s.
Therefore, this circuit is highly e±cient in area and delay. The contribution of this
paper advances the CAM memory design by minimal parameters including total
area, critical delay and latency to make the design cost-e±cient. The proposed
CAM architecture can be further extended for processor architectures in a three-
dimensional domain.
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