Approach to design a high performance fault-tolerant reversible ALU

Int. J. Circuits and Architecture Design, Vol. 2, No. 1, 2016 83
Copyright © 2016 Inderscience Enterprises Ltd.
Approach to design a high performance fault-tolerant
reversible ALU
Neeraj Kumar Misra*, Subodh Wairya and
Vinod Kumar Singh
Department of Electronics Engineering,
Institute of Engineering and Technology,
Lucknow, India
Email: neeraj.mishra@ietlucknow.ac.in
Email: swairya@ietlucknow.edu
Email: vksingh@ietlucknow.edu
*Corresponding author
Abstract: In the digital circuit design, the primary factors are low power and a
high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of
power consumption at nanoscale regime. Fault tolerant circuits are suited of
interruption of errors at the outputs. This manuscript focuses the design of ALU
in QCA-based and propose new parity preserving gate. It has been introduced
that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing
ALU. The ALU generates a number of arithmetic and logical function with
using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to
optimisation, the workability of UPPG gate is tested by QCA and the
simulation result obtained ensures the correctness of the design.
Keywords: reversible logic; parity preserving reversible gate; fault tolerant
arithmetic and logic unit; quantum cost; garbage output; quantum-dot cellular
automata; majority voter; MV; quantum computation.
Reference to this paper should be made as follows: Misra, N.K., Wairya, S.
and Singh, V.K. (2016) ‘Approach to design a high performance fault-tolerant
reversible ALU’, Int. J. Circuits and Architecture Design, Vol. 2, No. 1,
pp.83–103.
Biographical notes: Neeraj Kumar Misra is pursuing a PhD program under
TEQIP-II in the Department of Electronics Engineering at the Institute of
Engineering & Technology, (IET) Lucknow, U.P. He completed his BTech in
Electronics and Communication Engineering from Integral University and
MTech from Amity University, in 2008 and 2012 respectively. His research
interests include Reversible logic, fault-tolerant digital design, logic around
quantum-dot cellular automata, circuit and architectures for emerging
nanotechnology, low power VLSI.
Subodh Wairya is an Associate Professor of Electronics Engineering
department at the Institute of Engineering & Technology, (IET) Lucknow, U.P
India. He completed his Doctoral degree from Motilal Nehru National Institute
of Technology Allahabad, India and received his ME (Telecommunication)
from Jadavpur University, Kolkata and BTech (Electronics Engineering.) from
H.B.T.I., Kanpur, India. He has more than 20 years’ experience in teaching and

84 N.K. Misra et al.
research. He has served as Scientist ‘B’ in Defence Research & Development
Organisation (DRDO) and Graduate Engineer (Design Project) in Hindustan
Aeronautical Limited (HAL), Lucknow from 1994 to 1996.
Vinod Kumar Singh is Professor and Head in the Department of Electronics
Engineering at the Institute of Engineering & Technology, (IET) Lucknow, U.P
India. He has completed his Doctoral degree in the year 2004. He received his
BE and ME Electrical Engineering degrees from Motilal Nehru Regional
Engineering College, Allahabad, India, in 1977 and 1979 respectively. His
major research interests include analogue integrated circuits, digital circuits,
active and passive circuits, circuit theory and signal and systems. He has
published several research papers in IEEE (USA), IEEE (UK) and other
international journal. He has been a reviewer of IEEE Trans. on Circuits and
Systems-II Analog and Digital Signal Processing since 2000.
1 Introduction
Though integrated circuits technology has become popular nowadays, since everything
has its pros and cons, it also has high energy and power consumption as its drawback.
Hence, researchers want the new concept related to heat dissipation and low power.
Keyes and Landauer (1970) and Landauer (1961) proved that information bits those have
been lost dissipate n*(KTln2) joules of energy, where n is the summation of the losing
information bits, K is Boltzmann’s constant and T is the temperature at which is
operating (Landauer, 1961). Therefore, the energy loss is the primary concern in latest
technology. Bennett showed that no energy dissipation can be possible if we design
circuits using reversible gates (Bennett, 1973). To make more efficient use of the energy,
the technology i.e. reversible logic is compulsory to use for the forthcoming technology.
In reversible logic gate Boolean function, it computes is bijective – that is, every
distinct input pattern yields a distinct output pattern (Fredkin and Toffoli, 2002).That
signifies the input logic can be recovered from the outputs, but it is not capable to find
errors in the circuit. Fault-tolerant (FT) reversible structures are capable of error control
using parity check between input and output (Thapliyal and Ranganathan, 2009; Sen
et al., 2014a, 2014b; Misra et al., 2015). In digital systems, FT is controlled by parity
check. Therefore parity preserving feature is utilised to design FT ALU (Zhou et al.,
2015; Morrison and Ranganathan, 2011). Many methods for physical realisation of
quantum-dot cellular automata (QCA) cells are suggested such as molecular QCA (Lent
et al., 1993; Snider et al., 1998; Bernstein et al., 2004).
In this paper, we suggest a high performance, FT ALU in QCA framework. The main
purpose of this workaround proposed parity preserving gate, high performance, FT ALU
circuit and optimising QCA primitives as well as reversible primitives can be summarised
as follows:
1 Starting with the basic overview of reversible logic and QCA, and its state of art
section. We will show existing approaches of designing reversible ALU.

Approach to design a high performance fault-tolerant reversible ALU 85
2 Then, we proposed new type of 4 × 4 parity preserving gate named as UPPG gate to
optimise the design of the ALU.
3 We used the UPPG gate in synthesises parity preserving reversible XOR, NAND,
NOR, OR, AND, inverter and signal duplication operations.
4 We demonstrate the proposed UPPG gate is a FT reversible gate with lemmas.
5 We offered the circuit design of FT reversible ALU dealing with proposed reversible
UPPG gate. This prime design focuses on optimising the gate counts, constant
inputs, garbage outputs and quantum cost. A lemmas and algorithm are presented for
framing a FT ALU.
6 We presented the QCA cell layout, block diagram with clock zone and simulation
result of the proposed UPPG gate. The extracted QCA primitives (cell complexity,
latency, gate count, total area and cell area) are shown through tables and finally
concludes the paper.
2 Reversible logic and QCA basics
2.1 Reversible logic
In reversible logic gate Boolean functions, it computes is bijective that is every distinct
input pattern yields a distinct output pattern. That enlighten the inputs can be restored
from the outputs (Toffoli, 1980). The quantum cost of any reversible gate is an
optimising cost metric parameter in circuit synthesising (Thomsen et al., 2010). Any
reversible gate can decompose into primitive quantum gates, like a CNOT gate,
controlled V gate and controlled V+
gate (Figure 1).
Figure 1 Quantum basics, (a) CNOT gate (b) controlled-V gate (c) controlled-V+ gate
If A then
V(B) else B
A
P =
A
B If A then
else B
)
B
(
V+
A
P =
A
B V +
V
A
P =
A
B ⊕ B
A
Q ⊕
=
(a) (b) (c)
2.2 Parity preserving reversible logic gate
The elemental criteria of a parity preserving reversible logic gate have two conditions
preserves first is Iv {bijective mapping} Ov and the second is hamming weight of inputs
matches with the hamming weight of outputs. For an n × n parity preserving reversible
logic gate, it must preserve the criteria of (I1 ⊕ I2 ⊕ I3 …………, ⊕ In) = (O1 ⊕ O2
⊕ O3 …………, ⊕ In), where Iu and Ov are the input and output parity. The parity
preserving reversible gate will be useful for the design of fault-tolerant system (Sen et al.,
2012).

Figure 2 Existing parity preserving gates including F2G, FRG and NFT, (a) block diagram
(b) quantum equivalent
FRG
A
B
C
F2G
A
B
C
A
P =
AC
B
A
Q ⊕
=
C
A
AB
R ⊕
=
AC
B
A ⊕
C
A
AB⊕
A
A
B
C
A
B
A⊕
C
A⊕
A
P=
NFT
A
B
C
B
A
P ⊕
=
C
B
C
A
Q ⊕
=
BC
C
A
R ⊕
=
B
A⊕
C
B
C
A ⊕
BC
C
A ⊕
A
B
C
B
A
Q ⊕
=
C
A
R ⊕
=
A
B
C
(a) (b)
We present some existing parity preserving reversible gates that are used to design of
ALU circuits, like: Feynman double gate (F2G) with quantum cost of two, Fredkin gate
(FRG) with quantum cost of five and new fault tolerant gate (NFT) with quantum cost of
five is depicted as quantum implementation in Figure 2. A reversible logic gates F2G,
FRG and NFT are 3 × 3 type fault tolerant gate having mapping of its input to outputs is
bijective hence, all gates are reversible. The other feature is parity of input and
corresponding parity of output of the fault tolerant gate are matched. Figure 2(a) depicted
the block diagram of the FRG, F2G and NFT gate respectively.
2.3 Quantum-dot cellular automata
The fundamental unit of QCA device is a QCA cell with a set of four quantum-dots
placed at the corners of a square and contains two free electrons, depicted in Figure 3(c).
The electrons are curbed by potential barriers and can motion by tunnelling and curbed
the barrier potential and generate, binary logic value 1 (P = +1) and 0 (P = –1). At QCA
has four clock zones (phase shifted by 90°) are used to control the information flow in
QCA circuits as depicted in Figure 3(a). The basic gate in QCA device is a majority voter
gate, depicted in Figure 3(d). The majority voter gate consists of three input cell and one
drive cell that implement logical equation is Maj = AB + BC + CA. If we set polarisation
value either 1 or 0, we will design majority OR and AND gates respectively (Walus et al.,
2004; Chabi et al., 2014; Sen et al., 2014a). Some other important QCA gate is inverter as
depicted in Figure 3(b). In QCA wire crossing structures depicted in Figure 3(e).

Figure 3 QCA fundamentals, (a) QCA clock (b) QCA inverter (c) QCA basic cell (d) QCA
majority voter (e) QCA wire-crossing (f) QCA wire
Switch Hold Release Relax
Hold Release Relax
Switch
Time
0
0
1
1
(a) (b)
e
e
Binary state ‘0'
P= -1
Binary state ‘1'
P= +1
e
e
Localized
Electron
D
A
B
C
A
B
C
MV
)
C
,
B
,
A
(
M
aj
)
C
,
B
,
A
(
M
aj
(c) (d)
P = -1, Binary= ‘0’
Input = A
A
A
A
A
A
Input Output
Clock zone 0 Clock zone 1 Clock zone 2 Clock zone 3
Information flow
(e) (f)
2.4 FT logic
In a manner of design FT reversible structure parity of input and output are matched. This
feature is applied for fault detection. A fault tolerant reversible gate is also known as a
conservative gate (Sen et al., 2013, 2014a; Bruce et al., 2002).

3 State of the art
Various prominent researchers have done the expressive work in the existing field of
reversible ALU (Rakshith and Saligram, 2013; Guan et al., 2011; Sen et al., 2014c;
Morrison and Ranganathan, 2011; Moallem et al., 2014). Till now there has not been
done any specific work on the relative topic and no such high performance, FT ALU
design in nanotechnology like QCA framework. On the other hand some existing design
(Rakshith and Saligram, 2013) of ALU has a FT ALU with the basic reversible gate, but
it was not possible to decay the parameters for n-bit ALU, and hence the complexity of
circuit kept on increasing and they did not develop theorems related to the number of
gates, garbage outputs, constant input and quantum cost. Another approach of ALU has
an optimised design, but design is not FT (Guan et al., 2011; Moallem et al., 2014). Sen
et al. (2014b) design a 1-bit ALU uses RM gate and FG gate there are limitation firstly:
ALU design requires too much quantum cost, garbage output and constant input.
Secondly: design is not high performance (synthesis only 20 operations). Thirdly, ALU
circuit is shown only for 1-bit, generalisation of n-bit ALU is not proposed and the design
is not FT (Sen et al., 2014b). Finally, existing works have some benefit and drawback.
However, most of the approaches are not optimised reversible parameters and not
synthesise more numbered of arithmetic and logical operation.
4 Design procedure of FT n-bit reversible ALU
In this section, we project a high performance and improved version of FT ALU. ALU is
the core of the CPU of a computer. It performs arithmetic and logical operation
(Thomsen et al., 2010). To design a FT ALU, we introduce a new type of 4 × 4 UPPG
gate to optimise the circuit of the ALU. In order to less architecture complexity, we
design a group-based cells named as group-1 PP cell (in Section 4.2.1), group-2 PP cell
(in Section 4.2.2) and group-3 PP cell (in Section 4.2.3). These group’s cells are then
extensively used to design 1-bit, 2-bit and n-bit FT ALU.
4.1 Proposed 4 × 4 parity preserving reversible gate
In this sub-section, we design a new type of 4 × 4 type parity preserving reversible gate,
namely UPPG, depicted in Figure 4(a). The new type of gate is one through which means
one of the inputs (D) is also output (S = D) and three other outputs are P = A ⊕ B ⊕ D,
Q = A ⊕ CD and R = A ⊕ (C + D). The truth Table 1 show that every distinct input
pattern yields a distinct output pattern, which is bijective and meet the condition of
reversibility. The new gate (UPPG gate) is parity preserving, because the hamming
weight of input A ⊕ B ⊕ C ⊕ D matches the hamming weight of output P ⊕ Q ⊕ R ⊕ S.
We use this parity preserving gate in synthesising arbitrarily using Boolean functions.
The utility is shown by lemmas 1, 2, 3 and 4. Figure 4(b) depicted the quantum
equivalent circuit. The quantum cost and total logic calculation of UPPG are 7 and
4α + 1β, respectively.

Figure 4 Proposed UPPG gate, (a) block diagram (b) quantum equivalent circuit of UPPG gate
UPPG
A
B
C
D
D
B
A
P ⊕
⊕
=
CD
A
Q ⊕
=
)
D
C
(
A
R +
⊕
=
D
S=
(a)
A
B
C
D
D
B
A ⊕
⊕
CD
A⊕
)
D
C
(
A +
⊕
D
A
B
C
D
D
B
A ⊕
⊕
CD
A⊕
)
D
C
(
A +
⊕
D
(b)
Table 1 Truth table of UPPG gate
Input Output
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 1 0 1 1
0 0 1 0 0 0 1 0
0 0 1 1 1 1 1 1
0 1 0 0 1 0 0 0
0 1 0 1 0 0 1 1
0 1 1 0 1 0 1 0
0 1 1 1 0 1 1 1
1 0 0 0 1 1 1 0
1 0 0 1 0 1 0 1
1 0 1 0 1 1 0 0
1 0 1 1 0 0 0 1
1 1 0 0 0 1 1 0
1 1 0 1 1 1 0 1
1 1 1 0 0 1 0 0
1 1 1 1 1 0 0 1
Lemma 1: An UPPG gate simultaneously implements XOR, AND, OR and signal
duplication operation.
Proof: If we put input bit A = 0; and other three inputs are for the three bits to be added;
the UPPG gate simultaneously implements P = B ⊕ D, Q = CD, R = C + D and S = D.
Lemma 2: An UPPG gate simultaneously implements XNOR, NAND, NOR and Signal

Proof: If we put input bit A = 1; and other, three inputs are for the three bits to be added;
the UPPG gate simultaneously implements P B D, Q CD, R C D
= ⊕ = = + and S = D.
Lemma 3: A UPPG gate simultaneously implements NAND, NOR, Inverter and Signal
Proof: If we put input bit A = 1 and B = 0; and other, two inputs are for the two bits to be
added; the UPPG gate simultaneously implements P D, Q CD, R C D
= = = + and S = D.
Lemma 4: New type of UPPG gate is a FT reversible gate.
Proof: Proposed UPPG gate is 4 × 4 type reversible gate. The UPPG can be represented
as: IV = (A, B, C, D), OV = (P = (A ⊕ B ⊕ D), Q = (A ⊕ CD), R = A ⊕ (C + D), S = D).
We know that hamming weight of input and hamming weight of output have to be same
in any parity preserving or fault tolerant reversible gate. The hamming weight of input is
(A ⊕ B ⊕ C ⊕ D) output of UPPG gate is (A ⊕ B ⊕ D)(A ⊕ CD) ⊕ A ⊕ (C + D) ⊕ D =
A ⊕ B ⊕ D ⊕ CD ⊕ (C + D) ⊕ D A B CD (C D) D A B CD (C D)D
⊕ ⊕ ⊕ + ⊕ = ⊕ ⊕ ⊕ +
(C D)D A B CD CD A B C D.
+ + = ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕ Thus, hamming weight of output is
equal to hamming weight of input. Hence UPPG gate is a fault tolerant reversible gate.
4.2 New design of fault- tolerant 1-bit reversible ALU
A new design of 1-bit ALU consists of a proposed four cells (group-1 PP cell+ group-2
PP cell+ group-2 PP (cell)–1 + group-3 PP cell) each proposed cells are designed by using
parity preserving reversible gates.
4.2.1 Design procedure of group-1 PP cell
In this sub-section, we implement a Group-1 PP cell with lower bound of reversible
parameters (gate counts, constant inputs, garbage outputs and quantum cost), which
consists of two sub-cell named as an U_3N_F PP cell and U_3F PP cell. These cells are
collectively named as Group-1 PP cell. The U_3N_F PP design cell consist of five gate of
three types (3 × NFT + 1 × F2G + 1 × UPPG) and U_3F PP design cell consist of four
gate of three types (2 × F2G + 1 × FRG + 1 × UPPG), which are depicted in Figure 5.
The quantum cost (QC) of F2G, FRG, UPPG and NFT are 2, 5, 7 and 5 respectively.
Thus, the quantum cost of this group-1 PP cell is 40, because
QC(Group-1 PP cell) 3QC(F2G) 1QC(FRG) 2QC(UPPG) 3QC(NFT)
3 2 1 5 2 7 3 5 40
= + + +
= × + × + × + × =
The Group-1 PP cell takes two input operands (Ai, Bi) along with the four selector bits
(S0 to S3) as together they work to generate group-1 PP cell output (Xi, Yi) as implement
by using equations (1) and (2). The group-1 cell also produces (S0 to S3) as output for
fan-outs to succeeding cells means 1-bit ALU design helpful for design of n-bit ALU.
Figures 5 and 6 depicted the circuit structure and compressed block diagram of group-1
PP cell. The group-1 PP cell is executed the input operands (Ai, Bi) along with the
selector bits (S0 to S3) by following a logical combination as shown in Table 2.

i 2 i i 3 i i
X S A B S A B
= + (1)
i i 1 i 0 i
Y A S B S B
= + + (2)
Figure 5 Proposed circuit structure of group-1 PP cell
F2G
FRG
F2G
UPPG
F2G
NFT
0
S
NFT
NFT UPPG
0
S
1
S
i
A
0
1
1
GO
2
GO
8
GO
1
S
0
0
2
S
3
S
i
B
0
0
0
0
0
0
0
0
1
3
S
2
S
i
Y
6
~
5
GO
7
GO
i
X
3
GO
4
GO
9
GO
10
GO
12
~
11
GO
13
GO
U_3F
PP Cell
0
S
1
S
i
A
0
S
1
S
i
Y
U_3N_F
PP Cell
i
B
i
A
2
S
3
S
i
B
2
S
3
S
i
X
Figure 6 Compressed block diagram of group-1 PP cell
0
S
1
S
i
A
0
S
1
S
i
Y
U_3N_F
PP Cell
i
B
i
A
2
S
3
S
2
S
3
S
i
X
U_3F
PP Cell
Group-1
PP Cell
i
B
i
A
3
S
2
S
1
S
0
S
2
S
i
Y
0
S
1
S
3
S
i
X
i
B
Table 2 Functional table of group-1 PP cell
S0 S1 Associated output Yi S2 S3 Associated output Xi
0 0 Ai 0 0 1
0 1 Ai Bi
+ 0 1 AiBi
1 0 Ai Bi
+ 1 0 AiBi
1 1 0 1 1 Ai

4.2.2 Design procedures of group-2 PP cell
The group-1 PP cell outputs (Xi, Yi, S0, S1, S2, S3) and two more inputs (Ci–1, M) are
applied to group-2 PP cell. Where Ci–1 is the input carry of (i – 1)th
stage and M is mode
control bits for the ith
stage of the ALU. The group-2 PP cell generates four outputs (Xi,
Ci–1, Yi, Ci, M). The block diagram of group-2 cell is depicted in Figure 8. Group 2 PP
cell synthesis equations (3) and (4). The equation for carry-out (Ci) also included the
mode control bit (M), carry-in (Cin) and group-1 PP cell outputs (Xi, Yi). In starting phase
carry-in (Cin) and mode bit (M) processed to compute the output carry (C0) using
equation (5). The design of computing C0 performed by group-2 (cell)–1 (Figure 7). If set
M = 0 and Cin = 1 means arithmetic operations and M = 1 for logical operations. The
complete list of arithmetic and logical operations executed by the proposed design of the
ALU is depicted in Table 3.
i 0 in 0
C M X C Y True for i 1
= + + = (3)
i i i 1 i
C M X C Y True for i 2
−
= + + ≥ (4)
0 in
C C M
= + (5)
Table 3 Different function of fault-tolerant ALU
ALU output ALU input
Opcode results
Logical functions
(M = 1)
Arithmetic functions
(M = 0, Cin = 1)
S3 S2 S1 S0
Inverting A A A 0 0 0 0
NOR operation (AB) A + B 0 0 0 1
A inhibits B operation (A B)
+ A B
+ 0 0 1 0
Null operation 0 –1 0 0 1 1
NAND operation (A B)
+ A AB
+ 0 1 0 0
Inverting B B A B AB
+ + 0 1 0 1
XOR operation (A B)
⊕ A – B – 1 0 1 1 0
B inhibits A operation (A B)
+ AB 1
− 0 1 1 1
A implicates B operation (AB) A + AB 1 0 0 0
XNOR operation (A B)
⊕ A + B 1 0 0 1
Signal duplication of B B A B AB
+ + 1 0 1 0
AND (AB) AB – 1 1 0 1 1
Unity operation 1 A + A 1 1 0 0
B implicates A operation (AB) A + B + A 1 1 0 1
OR operation (A + B) A B A
+ + 1 1 1 0
Signal duplication of A A A – 1 1 1 1 1
In the design of group-2 PP (cell)–1 we use one F2G and one UPPG gates, which is
depicted in Figure 7. The quantum cost of group-2 PP (cell)–1 is 9, because
( )
–1
QC Group-2 PP(cell) 1QC(F2G) 1QC(UPPG)
1 2 1 7 9
= +
= × + × =

Figure 7 Block diagram of group-2 (cell)–1
UPPG
F2G
0 GO 0
0
1
in
C
in
C
M
GO
M
M
C
C in
0 +
=
Group-2
PP (Cell)-1
M M
in
C 0
C
The circuit description of a group-2 PP cell, consists of three gates of two types (1 × FRG
+ 2 × UPPG) which is depicted in Figure 8. The quantum cost of FRG and UPPG gates
are 5 and 7 respectively. Thus the quantum cost of group-2 PP cell is 19, because
QC(Group-2 PP cell) 1QC(FRG) 2QC(UPPG)
1 5 2 7 19
= +
= × + × =
Figure 8 Block diagram of group-2 PP cell
UPPG
FRG
i
X
0
i
X
1
i
C − GO 0
1
UPPG
M
0
0
i
Y
i
Y
GO GO
M
i
C
Group-2
PP Cell
i
Y
i
Y
M M
i
X
1
i
C −
i
C
i
X
4.2.3 Design procedure of group-3 PP cell
The group-3 PP cell uses the input of the previous design cells. It generates the output
function Zi = Xi ⊕ Yi ⊕ Ci. The design structure is depicted in Figure 9. Group-3 PP cell
uses one gate of one type (1 × UPPG gate).The quantum cost of UPPG gate is 7;
therefore the quantum cost of group-3 PP cell is equal with:
QC(Group-3 PP cell) 1QC(UPPG)
1 7 7
=
= × =
Figure 9 Block diagram of group-3 PP cell
UPPG
i
X
i
Y
0
i
C
Z
GO
Group-3
PP Cell
i
X
i
Y
i
C
Z
4.2.4 New design of fault tolerant n-bit reversible ALU
New FT, 2 and n-bit ALU are depicted in Figures 10 and 11 which includes four cells (n
× group-1 PP cell, n × group-2 PP cell, 1 × group-2 PP (cell)–1 and n × group-3 PP cell).
The algorithm for the design of n-bit fault tolerant ALU is given in Algorithm 1.

Figure 10 Proposed design of ft 2-bit ALU
Group-1
PP Cell
Group-2
PP Cell
Group-2 PP
(Cell)-1
F2G
Group-3
PP Cell
Group-1
PP Cell
Group-2
PP Cell
Group-3
PP Cell
0
Z0
Z1
0
B
0
A
3
S
2
S
1
S
0
S
0
X
in
C
0
Y
M
M
in
C
2
S
3
S
1
S
0
S
0
X
0
Y
0
C
1
C
2
S
3
S
1
S
0
S
1
X
1
C
1
Y
M
1
X
1
Y
1
C
M
2
C
1
B
1
A
0
0
Figure 11 Proposed design of n-bit fault- tolerant ALU
Group-1
PP Cell
Group-2
PP Cell
Group-2
PP (Cell)-1
F2G
Group-3
PP Cell
Group-1
PP Cell
Group-2
PP Cell
Group-3
PP Cell
M
M
0
M
Group-1
PP Cell
Group-2
PP Cell
Group-3
PP Cell
M
F2G
M
0
0
GO
0
GO
0
B
0
A
3
S
2
S
1
S
0
S
2
S
3
S
1
S
0
S
in
C
in
C
0
X
0
Y
0
Y
0
X
1
C
0
C
1
B
1
A 1
X
1
C
1
Y
1
X
1
Y
1
C
0
Z
1
Z
n
C
n
C
n
X
n
Y
1
n
C +
n
Z
n
X
n
C
n
Y
n
B
n
A
2
S
3
S
1
S
0
S

Algorithm 1 Reversible n-bit high performance FT ALU
1 Input: n: The number of bits used in the operands A and B.
Select group-1 PP cell and take an operand of inputs (An, An–1,……A2, A1),
(Bn, Bn–1, B2, B1) and four selector bits (S0, S1, S2, S3)
2 Output: (Zn, Zn–2….…,Z1): The outputs depends on the various combinations of selector bits.
3 Begin
For each Ai ∈ A and Bi ∈ B
4 Do statement
Stage 1 Selection of input operands (Ai, Bi) and selector bits (S0, S1, S2, S3) from Group-1
PP cell and generate outputs (Xi, Si, Yi,) where i 2 i i 3 i i
X S A B S A B
= + and
i i 1 i 0 i
Y A S B S B
= + + then associate to group-2 PP cell.
Stage 2 Select group-2 PP (cell)–1 and acquire inputs (M, Cin) and generate outputs M and
O in
C C M.
= + First output M is applied to the group-2 PP cell and C0 to group-3
PP cell.
Stage 3 Select group-3 PP cell and acquire input from previous cells (group-1 PP cell,
group-2 PP cell, group-2 PP (cell)–1) and will finally generate desired function
output Zi = Xi ⊕ Yi ⊕ Ci
Stage 4 Record each Zi
5 End for
6 End
5 Evaluation of the proposed FT ALU and discussion
Proposed fault-tolerant ALU design is more optimised than the existing design shown in
Rakshith and Saligram (2013), Guan et al. (2011) and Moallem et al. (2014). One of the
important factors of ALU design is its total logical calculation (TLC). We have shown
that our design is more efficient than the existing design with related to TLC. Hardware
complexity is premeditated by TLC. The proposed design of the ALU is made up of
fewer number of reversible gates like F2G, NFT, FRG and UPPG gates, which are
established on lower bound parameter such as TLC (T) and other optimised parameter
established by Lemmas 1, 2 and 3.
(F2G)
T 2
= α
(NFT)
T (1 ) (for P-expression) (1 2 2δ) (for Q-expression)
(1 2 1δ) (for R-expression)
3 4 3δ
= α + α + β +
+ α + β +
= α + β +
(FRG)
T (1 2 1δ) (for Q-expression) (1 2 1δ) (for R-expression)
2 4 2δ
= α + β + + α + β +
= α + β +

(UPPG)
T 2 for P-expression) (1 1 ) (for Q-expression)
(1 ) (for R-expression)
4 1
= α ( + α + β
+ α
= α + β
In the design of ALU we can use F2G for making fan-out. In the structure of ALU, the
TLC(T) for group-1 PP cell is 3 (2 )(for F2G)
3 (3 4 3δ) (for NFT) 1 (2 4 2δ)(for FRG)
2 (4 1 ) (for UPPG) (as Figure 5) 25 18 11δ
× α
+ × α + β + + × α + β +
+ × α + β = α + β +
T for group-2 PP cell is1 (2 4 2δ) (for FRG)
2 (4 1 ) (for UPPG) (as Figure 8)
10 6 2δ
× α + β +
+ × α + β
= α + β +
–1
T for group-2 PP(cell) is 1 (2 ) (for F2G gate)
1 (4 1 ) (for UPPG) (as Figure 7) 6 2
× α
+ × α + β = α + β
T for group-3 PP cell is1 (4 1 ) (for UPPG) (as Figure 9) 4 1
× α + β = α + β
Therefore, our novel fault-tolerant 2-bit ALU the TLC is:
( )
2-bit –1
T 2 (group-1 PP) 2 (group-2 PP) 1 group-2(cell)
2 group-3 PP 1 F2G
2 (25 18 11δ) 2 (10 6 2δ) 1 6 2 2 (4 1 ) 2
86 52 26δ (as Figure10)
= × + × + ×
+ ×( ) + ×
= × α + β + + × α + β + + ×( α + β) + × α + β + α
= α + β +
where
α two input XOR gate calculation
β two input AND gate calculation
δ NOT gate calculation.
Lemma 1: A reversible n-bit fault-tolerant ALU can be utilised with (14n + 2) reversible
gates; and (21n + 4) constant input where the n = number of data order
Proof: A group-1 cell includes nine gates (3 × F2G, 1 × FRG, 2 × UPPG and 3 × NFT),
group-2 includes three gates (1 × FRG and 2 × UPPG), group-2 (cell)–1 includes 2 gates
(1 × UPPG and 1 × F2G) and group-3 includes one gate (1 × UPPG). A 1-bit ALU is
constructed with (1 × group-1 cell, 1 × group-2 cell, 1 × group-3 cell, 1 × group-2 (cell)–1
and 1 × F2G). Hence, the total gate count (NOG) requires to design a 1, 2, 3 and n-bit
ALU is
(Group-1PP) (Group-2 PP) (Group-3 PP)
(Group-2 PP(Cell) 1 F2G
NOG(1-bit) NOG NOG NOG
NOG NOG
−
= + +
+ +
NOG(1-bit) (9 3 1) 2 1 16 (13 1) 2 (1)
= + + + + = = × + +
Hence, the statement true for the base case n = 1.

NOG(2-bit) 2 9 3 1 2 2 30 (13 2) 2 (2)
= ×( + + ) + + = = × + +
NOG(3-bit) 3 9 3 1 2 3 44 (13 3) 2 (3)
= ×( + + ) + + = = × + +
Assume that the statement true for n = m. Hence, an m-bit fault tolerant ALU can be
utilised with (14m + 2) gate count.
The group-1 cell produces 13 constant inputs, group-2 produces five constant inputs,
group-2 (cell)–1 produces 4 constant inputs and group-3 produces only one constant input.
The F2G produces two constant inputs. Hence, the total constant inputs produces by a 1,
2 and 3 bit ALU as follows.
(Group-1PP Cell) (Group-2 PP Cell) (Group-3 PP Cell)
(Group-2 PP (Cell) 1 F2G
CI(1-bit) CI CI CI
CI CI
−
= + +
+ +
CI(1-bit) (13 5 1) 4 2 25 19 1 4 2
= + + + + = = × + +
CI(2-bit) 2 13 5 1 4 4 46 19 2 4 4
= ×( + + ) + + = = × + +
CI(3-bit) 3 (11 5 1) 4 6 67 19 3 4 6
= × + + + + = = × + +
Assume that the statement true for n = m. Hence, an m-bit ALU produces at least 19m +
4 + 2m = (21m + 4) constant input.
Lemma 2: A reversible n-bit fault-tolerant ALU can be utilised with (22n + 3) garbage
output.
Proof: Proposed n-bit ALU includes four group cells (n × group-1 PP, 1 × group-2 PP
(cell)–1 n × group-2 PP and n × group-3 PP). The group-1 cell produces 13 garbage
output, group-2 (cell)–1 produces three garbage outputs, group-2 produces five garbage
outputs, group-3 produces three garbage output and the F2G produce one garbage
outputs. Hence, the total garbage outputs can be calculated as follows.
(Group-1 PP Cell) (Group-2 PP Cell) (Group-3 PP Cell)
(Group-2 PP (Cell) 1 F2G
GO(1-bit) GO GO GO
GO GO
−
= + +
+ +
GO(1-bit) (13 5 3) 3 1 25 21 1 3 1
= + + + + = = × + +
GO(2-bit) 2 13 5 3 3 2 47 (21 2) 3 2
= ×( + + ) + + = = × + +
GO(3-bit) 3 13 5 3 3 3 69 (21 3) 3 3
= ×( + + ) + + = = × + +
Assume that, the statement true for n = m. Hence, an m-bit fault-tolerant ALU uses
(22m + 3) garbage outputs.
Lemma 3: A reversible n-bit fault-tolerant ALU can be utilised with (66n + 9) quantum
cost.

Proof: A n-bit ALU constructed with four group cells (n × group-1 PP, 1 × group-2 PP
(cell)–1 n × group-2 PP and n × group-3 PP). The quantum cost of F2G, FRG, NFT, and
UPPG are 2, 5, 5 and 8 respectively. The group-1 cell produces 40 quantum cost, group-2
(cell)–1 produces nine quantum cost, group-2 produces 19 quantum cost, group-3
produces seven quantum cost and the F2G produce two quantum cost. Hence, the total
quantum cost can be calculated as follows.
(Group-1 PP Cell) (Group-2 PP Cell) (Group-3 PP Cell)
(Group-2 PP (Cell)–1 F2G
QC(1-bit) QC QC QC
QC QC
= + +
+ +
QC(1-bit) (40 19 7) 9 2 83 66 1 9 2
= + + + + = = × + +
QC(2-bit) 2 40 19 7 9 4 145 (66 2) 9 4
= ×( + + ) + + = = × + +
QC(3-bit) 3 (40 19 7) 9 6 213 (66 3) 9 6
= × + + + + = = × + +
Assume that, the statement true for n = m. Hence, an m-bit fault- tolerant ALU uses
(66m + 9 + 2m) = 68m + 9 quantum cost.
Figure 12 (a) UPPG gate block diagram with four clock zone (b) QCA cell layout of UPPG gate
(c) simulation result of UPPG gate (see online version for colours)
(a)

Figure 12 (a) UPPG gate block diagram with four clock zone (b) QCA cell layout of UPPG gate
(c) simulation result of UPPG gate (continued) (see online version for colours)
(b)
(c)

6 QCA implementation of UPPG gate
To delineate the use of new types of proposed UPPG gate in nanotechnology, we select
QCA. Since QCA rooted design has high computing speed, high packing density and no
loss of power in signal transition and propagation. It is extravagant that fan-out is not
accredited in reversible logic, but it has been acknowledged in molecular QCA (Thapliyal
and Ranganathan, 2009). The QCA layout of UPPG gate is depicted in Figure 12(b). This
QCA layout design with a 11 majority voter gate, six inverters, 233 cell complexity,
covers an area of 0.29 µm2
and clock cycle delay (latency) of 2.50. The QCA block
diagram of UPPG gate with four clock zone is depicted in Figure 12(a), which four clock
zone is represented by the number next to D (D0 = clock 0, D1 = clock 1, D2 = clock 2
and D3 = clock 4) and MV stand in the majority voter gate. The simulation to test the
workability of UPPG gate with QCA designer and follow the truth table of that gate
(Table 1). For the simulation result of UPPG gate is depicted in Figure 12(c). It has four
output waveform for P, Q, R and S. The first output signal P is obtained after 0.50 clock
cycle delay (latency), Q and R output after one clock cycle delay and the S output is zero
clock cycle delay. From Figure 12(c), we can see that polarisation value of all the four
output signals is fairly better.
7 The performance Tables 4, 5 and 6 of proposed design
It is explicitly from Table 5 that the proposed ALU design is more cost effective
compared to that of existing ALU design. Operational capacity of the proposed UPPG
gate is investigated by synthesising the most used functions such as AND, OR, XOR,
XNOR, NAND, NOR, inverter and signal duplication. A comparative performance result
of the proposed UPPG gate and the available reversible gate is stated in Table 4.The
Table 4 outcomes show that the proposed UPPG is more competent that the available
reversible gates in terms of operational capacity. Table 6 outlines the UPPG gate in QCA
cell layout in terms of complexity, latency, total area and cell area. We have used normal
cells with no any crossovers to enhance the QCA layout stability and efficiency. The
efficiency of UPPG gate layout structure can be confirmed by the cell complexity, total
area and latency. The proposed UPPG gate layout in QCA expressed by majority and
minority voter gate by equations (6), (7) and (8).
( )
P M(M(A, B, D), M(A, B, D), B A B D,
= = ⊕ ⊕ (6)
( ) ( )
( )
Q M M M(C, D, 0), A, 0 , M M(C, D, 0), A, 0 ,1 A CD,
= = ⊕ (7)
( ) ( )
( )
R M M M(C, D,1), A, 0 , M M(C, D,1), A, 0 ,1 A (C D)
= = ⊕ + (8)

Table 4 Performance comparison result of proposed and existing reversible gate
Operational capacity F2G FRG NFT TG PPHCG MIG UPPG (proposed)
XOR Yes No Yes No Yes Yes Yes
XNOR No No No No Yes No Yes
AND No Yes Yes Yes No Yes Yes
OR No No No Yes No No Yes
INVERTER No No Yes Yes No Yes Yes
Signal duplication Yes Yes No Yes Yes Yes Yes
NAND No No No No No Yes Yes
NOR No No No No No No Yes
TLC 2α 2α + 4β
+ 2δ
3α + 4β
+ 3δ
α + β 8α 3α + 2β
+ 1δ
4α + β
Total clock cycle 1σ 1σ 1σ 1σ 1σ 1σ 1σ
PPG Yes Yes Yes No Yes Yes Y
Table 5 The proposed ALU comparison to other previous circuits
Reversible designs NOG GO CI QC
Number of logical and
arithmetic operations
Fault tolerance
1-bit ALU: proposed 16 25 25 77 32 Yes
Rakshith and Saligram 17 37 33 595 32 Yes
Moallem et al. 6 5 4 25 12 No
Guan et al. 24 12 12 70 32 No
Morrison and Ranganathan 6 2 2 24 6 No
Sen et al. 14 15 10 135 20 No
Table 6 Performance analysis of proposed UPPG gate in QCA
Circuit
Gate count
(majority gate +
inverter)
Cell
coun
t
Latency
(clock
delay)
Total
area
(nm2
)
Cell
area
(nm2
)
Area
usage
(%)
UPPG
gate
11 majority gate +
6 inverters
233 0.50 + 1
+ 1 = 2.50
297,766 75,492 25.35
Notes: α – two input XOR calculation; β – two input and calculation; δ – not calculation;
σ – unit clock cycle; TLC – total logic calculation; PPG – parity preserving gate;
RGate – reversible gate; NOG – number of gates; GO – garbage outputs;
CI – constant input.
8 Conclusions
This paper is mainly focused on the proposed design of high performance fault-tolerant
reversible ALU. We have developed an algorithm to design fault-tolerant ALU. In
addition, we designed a new type of parity preserving gate (UPPG gate), which overcome
the shortcoming of few of 4 × 4 parity preserving gates that cannot synthesise any
Boolean functions but our proposed gate can do this. By using this, the ALU is designed

with various lemmas and correlated to reversible parameters. Finally, the high
performance, fault tolerant, 1-bit ALU is synthesised total 32 operations by using only
77 quantum cost and 16 gate count. It presents that the proposed ALU has the least gate
count over the existing design and produces only 25 garbage outputs. Moreover, it uses
only 25 constant inputs for implementing 16 logical and 16 arithmetic operations. We
have also presented UPPG gate in QCA framework. The cell layout design reflects that
233 cells, total area of only 29,7766 nm2
and use fewer numbers of the clock zone for
operating. The proposed parity preserving gate and high performance, fault-tolerant ALU
will be useful for implementing the low power digital circuits, nano-circuits in computer,
processor of the computer etc.
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