Thibault Grossi, Sr. Technology & Market Analyst, shares excerpts from the recently published report, Memory Processor Interface, Focus on CXL. The reports provides a taxonomy of CXL market segments and revenue forecasts through 2028.
Q1 Memory Fabric Forum: Compute Express Link (CXL) 3.1 UpdateMemory Fabric Forum
OCP Steering Committee member and ex-President of the CXL Consortium, Siamak Tavallaei, provides an update on the CXL specifications with a focus on the recently released 3.1 specification.
MemVerge CEO Charles Fan describes why memory-hungry generative AI is a driver for CXL technology, the new computing model for AI, and MemVerge software for CXL and AI.
Q1 Memory Fabric Forum: Intel Enabling Compute Express Link (CXL)Memory Fabric Forum
- Memory intensive workloads are dominating computing and increasing memory capacity just with CPU-attached DRAM is getting expensive.
- CXL allows augmenting system memory footprint at lower cost by running over existing PCIe links to add memory outside of the CPU package.
- Intel Xeon roadmap fully supports CXL starting with 5th Gen Xeons, and Intel CPUs offer unique hardware-based tiering modes between native DRAM and CXL memory without depending on the operating system.
- CXL has full industry support as the standard for coherent input/output.
Torry Steed, Sr. Product Marketing Manager at SMART Modular, provides an overview of CXL PCIe Add-in Cards (AICs) and memory modules that can be used to expand capacity in servers or in external memory pooling systems.
During the CXL Forum at OCP Global Summit, Dharmesh Jani of Meta and Siamak Tavalllei of the CXL Consortium describe the extensive work being done by the Open Compute Project related to CXL
Q1 Memory Fabric Forum: Compute Express Link (CXL) 3.1 UpdateMemory Fabric Forum
OCP Steering Committee member and ex-President of the CXL Consortium, Siamak Tavallaei, provides an update on the CXL specifications with a focus on the recently released 3.1 specification.
MemVerge CEO Charles Fan describes why memory-hungry generative AI is a driver for CXL technology, the new computing model for AI, and MemVerge software for CXL and AI.
Q1 Memory Fabric Forum: Intel Enabling Compute Express Link (CXL)Memory Fabric Forum
- Memory intensive workloads are dominating computing and increasing memory capacity just with CPU-attached DRAM is getting expensive.
- CXL allows augmenting system memory footprint at lower cost by running over existing PCIe links to add memory outside of the CPU package.
- Intel Xeon roadmap fully supports CXL starting with 5th Gen Xeons, and Intel CPUs offer unique hardware-based tiering modes between native DRAM and CXL memory without depending on the operating system.
- CXL has full industry support as the standard for coherent input/output.
Torry Steed, Sr. Product Marketing Manager at SMART Modular, provides an overview of CXL PCIe Add-in Cards (AICs) and memory modules that can be used to expand capacity in servers or in external memory pooling systems.
During the CXL Forum at OCP Global Summit, Dharmesh Jani of Meta and Siamak Tavalllei of the CXL Consortium describe the extensive work being done by the Open Compute Project related to CXL
CXL Memory Expansion, Pooling, Sharing, FAM Enablement, and SwitchingMemory Fabric Forum
The document discusses CXL, a new open standard protocol for efficient CPU and memory connectivity. CXL allows for memory disaggregation and pooling across devices by enabling high-bandwidth, low-latency connections between CPUs, GPUs, accelerators, and memory. This helps address the growing CPU-memory bottleneck by allowing expansion of memory capacity beyond what can physically connect to the CPU. CXL also enables memory tiering by providing different performance and cost options for "near" directly attached memory versus "far" switched or fabric attached memory.
During the CXL Forum at OCP Global Summit, Enfabrica CEO Rochan Sankar described how to bridge the network and memory worlds with their accelerated compute fabric switch.
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
In the CXL Forum Theater at SC23 hosted by MemVerge, the Open Compute Project provided an overview of CXL, as well as CXL-related hardware and software projects at OCP
During the CXL Forum at OCP Global Summit, memory system architect Jungmin Choi of SK hynix talks about the need for memory bandwidth and capacity, and the SK hynix Niagara solution.
All Presentations during CXL Forum at Flash Memory Summit 22Memory Fabric Forum
The document summarizes a full-day forum hosted by the CXL Consortium and MemVerge on CXL. The morning agenda includes presentations on CXL from representatives of Google, Intel, PCI-SIG, Marvell, Samsung, and Micron. The afternoon agenda includes panels on CXL usage models from Meta, OCP, Anthropic, and MemVerge. A keynote presentation provides an update on the CXL Consortium and the recently released CXL 3.0 specification, including its expanded fabric capabilities and management features. The specification is aimed at enabling new usage models for memory sharing and expansion to address industry trends toward increased data processing demands.
Shared Memory Centric Computing with CXL & OMIAllan Cantle
Discusses how CXL can be better utilized as a separate Fabric Cache domain to a processors own Local Cache Domain. This is done by leveraging a Shared Memory Centric architectures that utilize both the Open Memory Interface OMI, and Compute eXpress Link, CXL, for the memory ports.
Fugaku is a Japanese supercomputer utilizing Fujitsu's A64FX CPU. It was designed through an iterative co-design process between application developers and Fujitsu to achieve over 100x performance gain compared to the previous K computer within a 30-40MW power budget. The A64FX CPU utilizes 7nm technology and features 48 Arm-based cores with high bandwidth memory to achieve superior floating point and memory bandwidth performance efficiently. Early evaluations show Fugaku meeting performance and power targets and outperforming x86 processors for real applications.
During the CXL Forum at OCP Global Summit, SMART Modular Director Product Marketing Arthur Sainio, provides an overview of the company's CXL memory cards and modules.
During the CXL Forum at OCP Global Summit, Mahesh Wagh, CXL Consortium TTF Co-chair and Senior Fellow at AMD, presented and update of the CXL Consortium mission and road map.
Molex and Nvidia - Partnership to enable copper for the next generation artif...Memory Fabric Forum
During the CXL Forum at OCP Global Summit, Eddy Hwang of Nvidia and Wai Kong Poon of Molex presented a next-gen architecture for enabling copper for AI computing.
If AMD Adopted OMI in their EPYC ArchitectureAllan Cantle
AMD's EPYC Architecture has paved the way forward towards Heterogeneous Data Centric Computing, but it is still limited by it's parallel DDR interfaces. This presentation shows the potential for the EPYC architecture if it adopted the Open Memory Interface, OMI, for it's Near Memory interface.
Lightelligence: Optical CXL Interconnect for Large Scale Memory PoolingMemory Fabric Forum
During the CXL Forum at OCP Global Summit, Lightelligence Director of Engineering Ron Swatzentruber provides an overview of the company's optical port expander products and test results.
Arm: Enabling CXL devices within the Data Center with Arm SolutionsMemory Fabric Forum
During the CXL Forum at OCP Summit, Arm Director of Segment Marketing Parag Beeraka provides and overview of the Arm portfolio of CXL products for the Data Center
Apache Ignite vs Alluxio: Memory Speed Big Data AnalyticsDataWorks Summit
Apache Ignite vs Alluxio: Memory Speed Big Data Analytics - Apache Spark’s in memory capabilities catapulted it as the premier processing framework for Hadoop. Apache Ignite and Alluxio, both high-performance, integrated and distributed in-memory platform, takes Apache Spark to the next level by providing an even more powerful, faster and scalable platform to the most demanding data processing and analytic environments.
Speaker
Irfan Elahi, Consultant, Deloitte
In this deck, Yuichiro Ajima from Fujitsu presents: The Tofu Interconnect D.
"Through the development of post-K, which will be equipped with this CPU, Fujitsu will contribute to the resolution of social and scientific issues in such computer simulation fields as cutting-edge research, health and longevity, disaster prevention and mitigation, energy, as well as manufacturing, while enhancing industrial competitiveness and contributing to the creation of Society 5.0 by promoting applications in big data and AI fields."
Learn more: https://insidehpc.com/2018/08/fujitsu-unveils-details-post-k-supercomputer-processor-powered-arm/
and
http://www.fujitsu.com/jp/solutions/business-technology/tc/catalog/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
1) cuDNN is a library of deep learning primitives for GPUs that provides highly tuned implementations of routines such as convolutions, pooling, and activation layers.
2) Version 2 of cuDNN focuses on improved performance and new features for deep learning practitioners. It supports 3D datasets and new GPUs like Tegra X1.
3) cuDNN can be easily enabled in frameworks like Caffe and Torch by making minor changes to code and is compatible with APIs for deep learning routines.
The document summarizes IBM's Blue Gene/L supercomputer. It discusses that Blue Gene/L was created in 1999 through a partnership between IBM and Lawrence Livermore National Laboratory to build a scalable supercomputer optimized for bandwidth. It had 65,536 dual-processor nodes, 512 MB of memory per node, and used a 3D torus network topology to interconnect the nodes. Its main applications included protein folding, modeling the human brain, and other scientific problems.
This document discusses high performance computing with accelerators. It introduces accelerators like GPUs, FPGAs, and IBM's Cell processor that are used in supercomputers and computer clusters to accelerate computations. GPUs are well-suited for graphics and floating-point work, FPGAs for embedded and low-bit applications, and ClearSpeed's accelerators for matrix operations. While accelerators provide improved performance and efficiency over CPUs, programming them can be more difficult due to their specialized architectures.
Ecosystem Alliance Manager Michael Ocampo talks about the CXL industry's effort to break through the memory wall, memory bound use cases, CXL for modular shared infrastructure, and critical CXL collaboration that's happening now.
CXL Memory Expansion, Pooling, Sharing, FAM Enablement, and SwitchingMemory Fabric Forum
The document discusses CXL, a new open standard protocol for efficient CPU and memory connectivity. CXL allows for memory disaggregation and pooling across devices by enabling high-bandwidth, low-latency connections between CPUs, GPUs, accelerators, and memory. This helps address the growing CPU-memory bottleneck by allowing expansion of memory capacity beyond what can physically connect to the CPU. CXL also enables memory tiering by providing different performance and cost options for "near" directly attached memory versus "far" switched or fabric attached memory.
During the CXL Forum at OCP Global Summit, Enfabrica CEO Rochan Sankar described how to bridge the network and memory worlds with their accelerated compute fabric switch.
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
In the CXL Forum Theater at SC23 hosted by MemVerge, the Open Compute Project provided an overview of CXL, as well as CXL-related hardware and software projects at OCP
During the CXL Forum at OCP Global Summit, memory system architect Jungmin Choi of SK hynix talks about the need for memory bandwidth and capacity, and the SK hynix Niagara solution.
All Presentations during CXL Forum at Flash Memory Summit 22Memory Fabric Forum
The document summarizes a full-day forum hosted by the CXL Consortium and MemVerge on CXL. The morning agenda includes presentations on CXL from representatives of Google, Intel, PCI-SIG, Marvell, Samsung, and Micron. The afternoon agenda includes panels on CXL usage models from Meta, OCP, Anthropic, and MemVerge. A keynote presentation provides an update on the CXL Consortium and the recently released CXL 3.0 specification, including its expanded fabric capabilities and management features. The specification is aimed at enabling new usage models for memory sharing and expansion to address industry trends toward increased data processing demands.
Shared Memory Centric Computing with CXL & OMIAllan Cantle
Discusses how CXL can be better utilized as a separate Fabric Cache domain to a processors own Local Cache Domain. This is done by leveraging a Shared Memory Centric architectures that utilize both the Open Memory Interface OMI, and Compute eXpress Link, CXL, for the memory ports.
Fugaku is a Japanese supercomputer utilizing Fujitsu's A64FX CPU. It was designed through an iterative co-design process between application developers and Fujitsu to achieve over 100x performance gain compared to the previous K computer within a 30-40MW power budget. The A64FX CPU utilizes 7nm technology and features 48 Arm-based cores with high bandwidth memory to achieve superior floating point and memory bandwidth performance efficiently. Early evaluations show Fugaku meeting performance and power targets and outperforming x86 processors for real applications.
During the CXL Forum at OCP Global Summit, SMART Modular Director Product Marketing Arthur Sainio, provides an overview of the company's CXL memory cards and modules.
During the CXL Forum at OCP Global Summit, Mahesh Wagh, CXL Consortium TTF Co-chair and Senior Fellow at AMD, presented and update of the CXL Consortium mission and road map.
Molex and Nvidia - Partnership to enable copper for the next generation artif...Memory Fabric Forum
During the CXL Forum at OCP Global Summit, Eddy Hwang of Nvidia and Wai Kong Poon of Molex presented a next-gen architecture for enabling copper for AI computing.
If AMD Adopted OMI in their EPYC ArchitectureAllan Cantle
AMD's EPYC Architecture has paved the way forward towards Heterogeneous Data Centric Computing, but it is still limited by it's parallel DDR interfaces. This presentation shows the potential for the EPYC architecture if it adopted the Open Memory Interface, OMI, for it's Near Memory interface.
Lightelligence: Optical CXL Interconnect for Large Scale Memory PoolingMemory Fabric Forum
During the CXL Forum at OCP Global Summit, Lightelligence Director of Engineering Ron Swatzentruber provides an overview of the company's optical port expander products and test results.
Arm: Enabling CXL devices within the Data Center with Arm SolutionsMemory Fabric Forum
During the CXL Forum at OCP Summit, Arm Director of Segment Marketing Parag Beeraka provides and overview of the Arm portfolio of CXL products for the Data Center
Apache Ignite vs Alluxio: Memory Speed Big Data AnalyticsDataWorks Summit
Apache Ignite vs Alluxio: Memory Speed Big Data Analytics - Apache Spark’s in memory capabilities catapulted it as the premier processing framework for Hadoop. Apache Ignite and Alluxio, both high-performance, integrated and distributed in-memory platform, takes Apache Spark to the next level by providing an even more powerful, faster and scalable platform to the most demanding data processing and analytic environments.
Speaker
Irfan Elahi, Consultant, Deloitte
In this deck, Yuichiro Ajima from Fujitsu presents: The Tofu Interconnect D.
"Through the development of post-K, which will be equipped with this CPU, Fujitsu will contribute to the resolution of social and scientific issues in such computer simulation fields as cutting-edge research, health and longevity, disaster prevention and mitigation, energy, as well as manufacturing, while enhancing industrial competitiveness and contributing to the creation of Society 5.0 by promoting applications in big data and AI fields."
Learn more: https://insidehpc.com/2018/08/fujitsu-unveils-details-post-k-supercomputer-processor-powered-arm/
and
http://www.fujitsu.com/jp/solutions/business-technology/tc/catalog/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
1) cuDNN is a library of deep learning primitives for GPUs that provides highly tuned implementations of routines such as convolutions, pooling, and activation layers.
2) Version 2 of cuDNN focuses on improved performance and new features for deep learning practitioners. It supports 3D datasets and new GPUs like Tegra X1.
3) cuDNN can be easily enabled in frameworks like Caffe and Torch by making minor changes to code and is compatible with APIs for deep learning routines.
The document summarizes IBM's Blue Gene/L supercomputer. It discusses that Blue Gene/L was created in 1999 through a partnership between IBM and Lawrence Livermore National Laboratory to build a scalable supercomputer optimized for bandwidth. It had 65,536 dual-processor nodes, 512 MB of memory per node, and used a 3D torus network topology to interconnect the nodes. Its main applications included protein folding, modeling the human brain, and other scientific problems.
This document discusses high performance computing with accelerators. It introduces accelerators like GPUs, FPGAs, and IBM's Cell processor that are used in supercomputers and computer clusters to accelerate computations. GPUs are well-suited for graphics and floating-point work, FPGAs for embedded and low-bit applications, and ClearSpeed's accelerators for matrix operations. While accelerators provide improved performance and efficiency over CPUs, programming them can be more difficult due to their specialized architectures.
Ecosystem Alliance Manager Michael Ocampo talks about the CXL industry's effort to break through the memory wall, memory bound use cases, CXL for modular shared infrastructure, and critical CXL collaboration that's happening now.
Q1 Memory Fabric Forum: Memory expansion with CXL-Ready Systems and DevicesMemory Fabric Forum
Ravi Gummaluri, Director, CXL System Architecture at Micron describes use cases for memory expansion with tiered DRAM and CXL memory, along with performance data.
Q1 Memory Fabric Forum: Micron CXL-Compatible Memory ModulesMemory Fabric Forum
Michael Abraham, Director of Product Management at Micron, discusses data center challenges, the memory and storage hierarchy, Micron CZ120 memory modules, database (TPC-H) improvements, AI inferencing improvements, and how to enabling in your company.
Red hat Storage Day LA - Designing Ceph Clusters Using Intel-Based HardwareRed_Hat_Storage
This document discusses how data growth driven by mobile, social media, IoT, and big data/cloud is requiring a fundamental shift in storage cost structures from scale-up to scale-out architectures. It provides an overview of key storage technologies and workloads driving public cloud storage, and how Ceph can help deliver on the promise of the cloud by providing next generation storage architectures with flash to enable new capabilities in small footprints. It also illustrates the wide performance range Ceph can provide for different workloads and hardware configurations.
IBM DS8880 and IBM Z - Integrated by DesignStefan Lein
This Presentation shows the strength of the IBM DS8880 Enterprise Storage Platform with special emphasis on the System Z integration capabilities. December 2017
Q1 Memory Fabric Forum: Advantages of Optical CXL for Disaggregated Compute ...Memory Fabric Forum
Ron Swartzentruber, Director of Engineering at Lightelligence, explains why optical connectivity is needed for CXL fabrics, and provides an overview of the Photowave line of port expander PCIe cards and active optical cables.
During the CXL Forum at OCP Global Summit, MemVerge CEO Charles Fan presented accomplishments of the CXL industry since 2019, the development of concept cars occurring today, and his predictions for the future of CXL
Supermicro Servers with Micron DDR5 & SSDs: Accelerating Real World WorkloadsRebekah Rodriguez
This document provides an overview of Supermicro's comprehensive server portfolio, including their rackmount, cloud, and mainstream server solutions. It highlights several multi-node server platforms like BigTwin, FatTwin, and GrandTwin. The document also mentions Supermicro will have many options for the upcoming 4th generation AMD EPYC 'Genoa' platform with support for up to 96 cores, 128 PCIe lanes, and DDR5 memory at up to 6TB capacity. In summary, the document outlines Supermicro's server product lines and upcoming support for the high-end 4th generation AMD EPYC processors.
During the CXL Forum at OCP Global Summit, Michael Ocampo of Astera Labs explained the problem of the memory wall, and how CXL memory powered by Astera Labs can break through
Heterogeneous Computing : The Future of SystemsAnand Haridass
Charts from NITK-IBM Computer Systems Research Group (NCSRG)
- Dennard Scaling,Moore's Law, OpenPOWER, Storage Class Memory, FPGA, GPU, CAPI, OpenCAPI, nVidia nvlink, Google Microsoft Heterogeneous system usage
The document discusses testing done by IBM to evaluate the performance improvements provided by the IBM MAX5 memory expansion technology. The testing showed that by adding 512GB of memory via a MAX5 unit, increasing total memory to 1TB, the following benefits were achieved:
- Response time for business intelligence reports was 1.5-2.8 times faster.
- The cost of producing business intelligence reports could be decreased by 31%-64% over 3 years.
- The throughput of web-facing applications was 2.4-4.9 times greater.
- Read/write response time was decreased by 60%-80%.
Supermicro AI Pod that’s Super Simple, Super Scalable, and Super AffordableRebekah Rodriguez
The worlds of HPC and AI are evolving at a tremendous rate. The demands of modern-day applications put immense pressure on local IT teams and resources. More often than not, this pressure can come from requiring an AI strategy to speed up mission-critical applications - but this can come at a cost which can hinder adoption. In this webinar, Supermicro, together with International Computer Concepts (ICC) and Define Tech, will demonstrate their AI Super Pod that delivers on AI strategy needs without breaking the bank.
In the CXL Forum Theater at SC23 hosted by MemVerge, Lightelligence describes CXL's need for optical connectivity and their portfolio of CXL optical expander cards and cables
CXL is enabling new memory architectures by connecting CPUs and GPUs to shared memory pools. Early CXL 1.1 focused on memory expansion by connecting processors to DRAM modules. CXL 2.0 allowed for small memory pools accessible by a few servers. CXL 3.0 supports larger shared memory fabrics by connecting thousands of nodes and enabling true shared memory regions accessible coherently by multiple hosts and accelerators. However, shared memory fabrics using CXL 3.0 may experience greater latency variability and congestion compared to single-host or small memory pooling configurations.
Similar to Q1 Memory Fabric Forum: Memory Processor Interface 2023, Focus on CXL (20)
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Nilesh Shah provide an overview of the ZeroPoint portable, hardware IP portfolio for lossless memory compression and compaction. The IP boosts memory capacity 2-4x, bandwidth and performance/watt by 50%, and is 1,000x faster than competitors.
Q1 Memory Fabric Forum: Building Fast and Secure Chips with CXL IPMemory Fabric Forum
Gary Ruggles, Sr Product Manger for PCIe and CXL Controller IP, provides an provides example use cases for adoption of CXL, an introduction to Synopsys CXL IP Solutions, interop and proof points.
Q1 Memory Fabric Forum: Using CXL with AI Applications - Steve Scargall.pptxMemory Fabric Forum
MemVerge product manager and software architect Steve Scargall discusses key factors related to the use of CXL with AI apps including, memory expansion form factors, latency and bandwidth memory placement strategies, RDBMS investigation and results, vector database investigation, and results understanding your application behavior.
Q1 Memory Fabric Forum: CXL-Related Activities within OCPMemory Fabric Forum
OCP steering committee member, and former President of the CXL Consortium, Siamak Tavallaei, provides an overview of CXL-related activities happening within the Open Compute Project.
Q1 Memory Fabric Forum: CXL Controller by Montage TechnologyMemory Fabric Forum
For CXL AIC and memory module designers, Nilesh Shah of Montage provides and overview of their CXL memory controller product, technology, and performance.
Nick Kriczsky and Gorden Getty provide an overview of Teledyne LeCroy’s Austin Labs portfolio of products to services including: 1) testing for protocol and electrical compliance, interoperability, data integrity, and performance, 2) In depth protocol training (PCIe, USB, NVMe, NVMe-oF, Fibre Channel), and 3) Automation (solutions for analysis, jamming, generation)
Torry Steed, Sr. Staff Product Manager at SMART Modular, covers the changing shape of memory leading to new categories of CXL form factors. He dives deeper to address EDSFF and AIC variations, mechanical sizes, installation locations, capacity considerations, and power ratings.
Q1 Memory Fabric Forum: Memory Fabric in a Composable SystemMemory Fabric Forum
Eddie McMorrow, Sr. Product Manager at GigaIO, defines composable infrastructure and memory fabrics, then provides and overview of the FabreX memory fabric.
Arvind Jagannath of VMware makes the case for bridging the CPU-Memory imbalance with memory tiering, describes their vision for memory disaggregation, and explains that VMware will support CXL Expanders – Specific Configurations, Memory Tiering to reduce overall TCO, and Memory Accelerators to enable CXL-based use-cases.
MemVerge Field CTO Yong Tian shows what memory expansion costs with an analysis of various server configurations with up to 8TB of tiered DRAM and CXL memory.
Synopsys: Achieve First Pass Silicon Success with Synopsys CXL IP SolutionsMemory Fabric Forum
This document discusses Synopsys' CXL IP solutions for enabling first pass silicon success. It provides an overview of:
- How large data sets are driving the need for CXL and larger, more efficient cache coherent storage.
- How CXL allows memory expansion by enabling one interface to connect to various memory types like DDR, LPDDR, and persistent memory.
- Synopsys' complete CXL IP solution which uses proven PCIe IP to provide a highly efficient 512-bit controller and 32GT/s PHY for maximum bandwidth and low latency.
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In the CXL Forum Theater at SC23 hosted by MemVerge, Samsung described their the architecture and use cases of their hybrid drive that includes DRAM and Flash memory
Project Gismo introduces a global I/O-free shared memory object (Gismo) library that utilizes CXL to provide direct memory access across nodes. This allows distributed applications to access remote objects as fast as local memory, eliminating object serialization and data copying. Demo results show Gismo can improve performance of AI/ML workloads like Ray by up to 675% and reduce database synchronization times. The Gismo API provides functions to connect, create, access, and manage shared memory objects globally without I/O.
Enchancing adoption of Open Source Libraries. A case study on Albumentations.AIVladimir Iglovikov, Ph.D.
Presented by Vladimir Iglovikov:
- https://www.linkedin.com/in/iglovikov/
- https://x.com/viglovikov
- https://www.instagram.com/ternaus/
This presentation delves into the journey of Albumentations.ai, a highly successful open-source library for data augmentation.
Created out of a necessity for superior performance in Kaggle competitions, Albumentations has grown to become a widely used tool among data scientists and machine learning practitioners.
This case study covers various aspects, including:
People: The contributors and community that have supported Albumentations.
Metrics: The success indicators such as downloads, daily active users, GitHub stars, and financial contributions.
Challenges: The hurdles in monetizing open-source projects and measuring user engagement.
Development Practices: Best practices for creating, maintaining, and scaling open-source libraries, including code hygiene, CI/CD, and fast iteration.
Community Building: Strategies for making adoption easy, iterating quickly, and fostering a vibrant, engaged community.
Marketing: Both online and offline marketing tactics, focusing on real, impactful interactions and collaborations.
Mental Health: Maintaining balance and not feeling pressured by user demands.
Key insights include the importance of automation, making the adoption process seamless, and leveraging offline interactions for marketing. The presentation also emphasizes the need for continuous small improvements and building a friendly, inclusive community that contributes to the project's growth.
Vladimir Iglovikov brings his extensive experience as a Kaggle Grandmaster, ex-Staff ML Engineer at Lyft, sharing valuable lessons and practical advice for anyone looking to enhance the adoption of their open-source projects.
Explore more about Albumentations and join the community at:
GitHub: https://github.com/albumentations-team/albumentations
Website: https://albumentations.ai/
LinkedIn: https://www.linkedin.com/company/100504475
Twitter: https://x.com/albumentations
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2. ABOUT THE AUTHORS
2
Memory Fabric Forum | www.yolegroup.com
Principal Analyst
Simone.bertolazzi@yolegroup.com
John Lorenz
Senior Analyst
john.lorenz@yolegroup.com
Thibault GROSSI Lead author
Senior Analyst
Thibault.grossi@yolegroup.com
Emilie JOLIVET
Division Director
Emilie.jolivet@yolegroup.com
Simone BERTOLAZZI
3. A WIDE RANGE OF INFORMATION SOURCES
Our unique
position
allows us to
obtain
detailed and
accurate
information
to meet your
needs.
5,000 players
interviews
per year
120+ annual
conferences
100+
analysts
worldwide
6,800+
companies’
news relayed
25 years in the
semiconductor
industry
1250+ teardown
tracks available
3
Memory Fabric Forum | www.yolegroup.com
4. FIELDS OF EXPERTISE COVERING THE SEMICONDUCTOR INDUSTRY
4
Memory Fabric Forum | www.yolegroup.com
• Semiconductor Packaging
• Semiconductor Manufacturing
Equipment
• Memory
• Computing and Software
• Radio Frequency
• Compound Semiconductor
• Power Electronics
• Battery
• Photonics & Lighting
• Imaging
• Sensing & Actuating
• Display
• Electronic Systems
• Emerging Technologies
6. 6
CURRENT AND FUTURE KEY DATA CENTER CHALLENGES
Critical requirements
0 Failure
objective
This means high reliability and total redundancy
(internet connection, power, cables, hardware capacity,
cooling systems, etc.). Each failure could cost tens of
thousands to millions of dollars, depending on
business size and data availability requirements. It is
measured with data center tier segmentation.
High level of
security
High
bandwidth
internet
connection
Both top cybersecurity level and near military physical
security level.
Very reliable internet connection and very high
bandwidth (often similar to submarine communication
cable). It is needed to allow for high data flow.
Low power
consumption
A lot of energy is needed to power all the
infrastructure. In this context, managing and
optimizing power consumption is critical.
Technical breakthroughs
High cooling
capacity
Advanced, energy-efficient cooling solutions are
needed.
All level
redundancy
Redundancy is needed at all levels to provide a
maximum level of resilience.
High storage
capacity
Need to store an ever-increasing amount of data.
High density To store and process ever more data in a fixed volume.
Memory
bottlenecks
Optimizing data flow between memory and
processing units. Bringing them as close together as
possible or further optimizing memory and storage
tiering.
Lifespan and
maintenance
Easy and efficient maintenance increases resilience,
and a long lifespan decreases costs.
Memory Fabric Forum | www.yolegroup.com
Main Rational for CXL adoption
7. • Big latency and capacity gaps exist between memory and storage devices. In the last years,
various emerging technologies (e.g., 3D XPoint) have been in the works to fill this gap in order to
boost computing performance at the system level.
• In terms of scaling, logic processing technologies have advanced faster than memory. The
memory-logic performance gap has become more evident in the last decade.
• Since 2012, the average number of cores per server has increased ~3 times, reducing the
memory bandwidth available per core.
• The DRAM spending per server has progressively increased: it went up from ~15% of the server
ASP in 2015 to ~28% in 2022.
• This trend is expected to continue in the next five years.
• Memory stranding is a common issue in server architectures. It occurs when cores are fully
allocated, but unrented memory remains, leading to inefficient use of memory resources.
• At the cloud scale, memory stranding translates into costly resources remaining idle during
operation.
• Among the workloads driving the development of the data center market, high-performance
computing (HPC) and AI/ML models, which are memory capacity sensitive, are rapidly
increasing in complexity. For instance, In the Natural Language Processing (NLP) models, the
number of parameters increases by 14x per year.
MEMORY CHALLENGES AND BOTTLENECKS IN THE DATA CENTER
7
Memory Fabric Forum | www.yolegroup.com
An overview
Open System
Interconnects
such as CXL (see
next chapter),
which is getting
broad support
from leading
players in the
industry, could
tackle most of
these bottlenecks
and revolutionize
computing
architectures for
data centers.
Cost of memory per
server is increasing
Memory stranding
Workloads are
growing in
complexity
Memory hierarchy
needs further
optimization
Memory bandwidth
per core is
decreasing
3
2
1
4
5
8. Memory Fabric Forum | www.yolegroup.com
COMPUTE EXPRESS LINK (CXL) –DEVICE TYPES
DIMM
Accelerator
NIC
Cache
Processor
DIMM
DIMM
Accelerator
Cache
Processor
DIMM
Memory
Memory
Source: CXL Consortium
DIMM
Memory Buffer
Processor
DIMM
Memory
Memory
Memory
Memory
Type 1
for accelerators with no local
memory, such as Network
Interface Cards (NIC).
Through CXL.io and
CXL.cache, those devices can
access memory attached to
host processors.
Type 2
in this case, accelerators such
as GPUs, FPGAs, and ASICs
that have their own DDR or
HBM employ all three CXL
protocols to make the
processor’s memory available
for the accelerator.
Type 3
provides memory expansion
thanks to CXL.io and
CXL.memory. A buffer
attached to the CXL bus
provides capacity and
bandwidth extension to the
processing unit.
Memory expansion to (x)PUs
Yole area of focus
CXL.io + CXL.cache CXL.io + CXL.cache + CXL.mem CXL.io + CXL.mem
Through a combination of the CXL protocols (CXL.io, CXL.cache, CXL.mem), three use cases are possible:
8
9. MEMORY EXPANSION, POOLING, AND DISAGGREGATION USING CXL INTEGRATION
9
CXL 1.1 In-server memory expansion
(server level)
CPU
DIMM
CXL
memory
controller
DDR
DIMM
DDR
CXL over
PCIe 5.0
Memory
Memory
Memory
Memory
DDR DDR
CXL
Memory expander
CXL 2.0 Memory pooling
(rack level)
CXL 3.1 Fully disaggregation and
composability of resources
(rack-to-rack)
CPU
DIMM banks
DDR
CPU
DDR
CPU
DDR
Orchestration
and fabrics
management
DIMM Bank
CXL
memory
expander
CXL
memory
expander
CXL
memory
expander
Memory pool
CXL switch
CXL over PCIe 5.0
CXL over PCIe 5.0
Source: CXL Consortium
CXL: Compute Express Link
CPU pool
DPU pool
GPU pool
Memory
pool
storage
pool
CXL over
PCIe 6.0
Server 1 Server 2 Server 3
Memory Fabric Forum | www.yolegroup.com
10. Memory Fabric Forum | www.yolegroup.com
MEMORY AND STORAGE TECHNOLOGIES LEVERAGING CXL
CXLZ
3- Memory Pooling (ENVM
and NAND Flash-based)
2- Memory Pooling
(DRAM-based)
1- Direct Attached CXL
Memory Expanders
3) Storage Class Memory (SCM),
CXL SSDs
1) CXL Memory Expanders
2) Persistent memory
Latency
Register
Cache
HBM
DDR
SSD
<1ns
<10ns
<100ns
<100ns
~ 1000 x
GAP
HDD
10s µs
to few ms
100ms
10
11. CXL MEMORY EXPANDER FORM FACTOR
11
Memory Fabric Forum | www.yolegroup.com
EDSFF E3.S Drive
Source: Samsung
Source: Astera Labs
CXL
Memory
Controller
DIMM Slot
DIMM Slot
DIMM Slot
DIMM Slot
Add In Card + DRAM DIMM
Add In Card
• Can be tuned to the capacity needed and possibly
reusing DDR4 DIMMs
• Existing and robust form factor standard,
making it more convenient for future server
chassis architecture.
-
5.00
10.00
15.00
0%
20%
40%
60%
80%
100%
2022 2023 2024 2025 2026 2027 2028
CXL memory expander volumes (Munits)
Break down by form factor (%)
Add-In Card
Drives
Total
12. 12
Memory Fabric Forum | www.yolegroup.com
SERVER CPU, CXL MEMORY EXPANDERS TYPES AND USE CASES
A roadmap overview
Nov 2022,
EPYC GENOA, CXL 1.1
Jan 2023,
Sapphire Rapids, CXL 1.1
Q4 2023,
Emerald Rapids, CXL 2.0
2.0
2024,
EPYC Turin, CXL 2.0
2025 ?
EPYC Venice, CXL 3.0
2025 ?
Diamonds Rapids, CXL 3.0
CXL 1.1 CXL 2.0 CXL 3.0
CXL Drive – x8 PCIe lanes
CXL Drive – x4 PCIe lanes
CXL Add-in Card (x16 PCIe lanes)
Direct Attached Memory expander
Memory pooling behind switch
2022-2023 2024 - 2025 2025- 2026
Memory expander types
Use cases
Server CPU
Multi-headed memory pooling
13. DRAM EXPANDER MARKET FORECAST 2022 - 2028
Breakdown by use case and form factor
13
Memory Fabric Forum | www.yolegroup.com
2022
$1.7M
2022
$ 1.7M
2028
$15B
2028
$ 15B
Breakdown by format
Breakdown by use case
30%
70%
Drives
Add-In Card
87%
13%
100%
0%
Direct attached
memory expansion
Memory Pooling
25%
75%
14. CXL ADOPTION MILESTONES
14
Memory Fabric Forum | www.yolegroup.com
Estimated timeline
CXL could
revolutionize
the way
memory is
utilized and
accessed,
possibly
enabling the
rise of an
entire
industry
Services
Server memory
expansion
Memory pool:
• Memory utilization optimization
• Remove memory capacity limits
Memory pool:
• Ability to extend accelerator memory
• Ability to cascade switch and extend
CXL memory fabric
New memory technology.
• Rise of CXL SSD and ENVM
with thin data granularity
AI Server
HPC Server
Cloud and hyperscale servers
In memory database and analytics
Memory as a service
Software
Systems
CXL 1.1 CXL 2.0 CXL 3.1
CXL
adoption
Time
15. 2022-2028 CXL MARKET REVENUE FORECAST
$15B
$12.5B
$1.9B
$1.5B
$1.7M
$0.2
M $1M
15
CXL DRAM
CXL memory expander controller
CXL memory expander*
CXL switch
2022
$1.7M
2028
$15.8B
*inclusive of DRAM and CXL memory expander controller
CXL : Compute Express Link
$741M
$112
M
$143M
$583 M
2026
$2.1B
Memory Fabric Forum | www.yolegroup.com
16. 16
Memory Fabric Forum | www.yolegroup.com
COMPUTE EXPRESS LINK (CXL) – KEY TAKEAWAYS
Opportunities and threats of CXL deployment
Tailwinds Headwinds
• Cost?
• Delay on CXL capable CPU
roadmap
• Macroeconomic conditions
• Security concerns
• Reliability
• Large support from the
industry
• Datacenter memory
bottleneck and challenges.
• Enable full server disagregation
and composability.
17. 17
Memory Fabric Forum | www.yolegroup.com
LET’S TALK ABOUT COST
2x
16 x 128GB DRAM DIMM
2x
8 x 128GB DRAM DIMM
8x
Pool of 16 x 512GB DRAM CXL exp
2x
+
8x
8x
Pool x 16 x 128GB DRAM CXL exp
1x
+
2x
8 x 128GB DRAM DIMM
Total DRAM
32TB
32TB
Total DRAM
accessible
per server
Estimated
cost
difference
18TB 4TB
18TB
4TB
+10%
-35%
*Considering RDIMM + JBOM+ CXL drives
1
2
3
Conventionnal
Capacity
optimized
Cost
optimized