This document discusses advanced logic circuits including pseudo-NMOS logic, pass-transistor logic, dynamic MOS logic, emitter-coupled logic (ECL), and BiCMOS digital circuits. Pseudo-NMOS logic uses one transistor per input instead of two to reduce area and delay. Pass-transistor logic builds logic functions using NMOS or transmission gate switches. Dynamic MOS logic uses precharge and evaluate phases to reduce static power at the cost of increased sensitivity to noise. ECL uses differential pairs for noise immunity and constant current sources. BiCMOS combines CMOS and BJTs to achieve high performance with lower power than ECL.

1.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 19/21/2020
Advanced MOS and Bipolar Logic
Circuits
Chapter 14

2.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 29/21/2020
INTRODUCTION

3.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 39/21/2020
Standard CMOS is Excellent. However:
2 Trns/Input →↑ Silicon Area →↑ 𝐶 →↑ 𝑡 𝑃
Additional forms are required

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PSEUDO-NMOS LOGIC CIRCUITS

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INTRODUCTION

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Pseudo-NMOS Logic Circuit
CMOS: 2 Transistors/input
→ ↑C → ↑(tp & PD_dynamic)
Use one network. Which?Keep PDN, & replace
PUN W/ a perm on MOS.
PMOS: 1 Transistors/input

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Pseudo-NMOS Inverter
CMOS

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Pseudo-NMOS Inverter

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Pseudo-NMOS Logic Circuit
PDN
Active Load

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Pseudo-NMOS Logic Inverter I-V
Characteristics
iD
Qn

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Qn
Qp
iD
Pseudo-NMOS Logic Inverter I-V
Characteristics

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Qn vi = 0 V
iD
Pseudo-NMOS Logic Inverter I-V
Characteristics

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Qn
iD
Qp
Pseudo-NMOS Logic Inverter I-V
Characteristics

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NOR Gate of the Pseudo-NMOS

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NAND Gates of the Pseudo-NMOS

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PASS-TRANSISTOR LOGIC CIRCUITS

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PASS-TRANSISTOR LOGIC (PTL)
CIRCUITS
Building the logic functions using switches

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Y = ABC
PASS-TRANSISTOR LOGIC (PTL)
CIRCUITS

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Y = A(B + C)
PASS-TRANSISTOR LOGIC (PTL)
CIRCUITS

20.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 259/21/2020
PASS-TRANSISTOR LOGIC (PTL)
CIRCUITS
Building the logic functions using switches
1. Either NMOS
2. Or Transmission Gates

21.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 279/21/2020
An Essential Design Requirement
Every node have, at all times, a low-resistance path to either
ground or VDD
×

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An Essential Design Requirement
Every node have, at all times, a low-resistance path to either
ground or VDD
√

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GS tV V
poor 1
Operation with NMOS Transistors as
Switches

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poor 1
On
Operation with NMOS Transistors as
Switches

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Operation with NMOS Transistors as
Switches

26.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 329/21/2020
0 0
DDV
On
Off
DDV
Off
Restoring VDD

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0
DDV
On
Off
DDV
Off
Restoring VDD
Off
On
V
On
DDV DDV
poor 1
tV
+ve feedback around
the inverter
Use zero-threshold
Devices instead
↑ 𝑃𝐷𝑆𝑡𝑎𝑡𝑖𝑐

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The Use of CMOS Transmission Gates as
Switches

29.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 359/21/2020
GSV
OV
GSV
The Use of CMOS Transmission Gates as
Switches

30.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 369/21/2020
DDV
GSV
GSV
The Use of CMOS Transmission Gates as
Switches
OV DDV

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Two-to-One Multiplexer

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Two-to-One Multiplexer

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Realization Of The XOR Function

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Realization Of The XOR Function

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Realization Of The XOR Function
XNOR

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Complementary Pass-Transistor Logic

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DYNAMIC MOS LOGIC CIRCUITS

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Basic Principle
Advantages:
1. No static power dissipation ( CMOS)
2. ↓ # of transistors, chip area, C, & tp (PsNMOS.

39.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 469/21/2020
Parasitic Capacitances Charge Leakage
Periodic Refreshment
VO
Dynamic
Basic Principle

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On
Off
VDD
Δ
Δ
Δ
Basic Principle
Precharge Phase
0
0

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1
1
Off
On
Off
×
Basic Principle
Evaluation Phase
On?
VDD0
Δ
Δ
Δ

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Example

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Nonideal Effects
Noise Margins
NMOS starts to conduct at VI = Vt
IL IH tV V V 
L tNM V
H DD tNM V V 
tNM V 

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Output Voltage Decay Due To Leakage Effects
Nonideal Effects
VDD
Off

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Charge Sharing
VDD ↓
Nonideal Effects
Evaluation Phase 0Precharge Phase
To replenish lost charge

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Nonideal Effects
Charge Sharing
Static Power Dissipation
To replenish lost charge

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Off
0
On
0
VDD VDD
Off
0
On
0
VDD
On
Precharge
On
Cascading Dynamic logic Gates

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Off
1
On
1
VDD VDD
Off
1
On
1
VDD
On
Evaluate
On
Cascading Dynamic logic Gates
On
Off
On
Off
↓VDD ↓VDD< Vt
Off
< VDD
×VDD
0

49.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 589/21/2020
During evaluation, Y:
1. Either remains low ≈ 0 V
2. A 0-to-1 transition.
Domino CMOS Logic

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Off
On
VDD VDD
Off
On
VDD
OffOn
00
0 0
0 0
Precharge
Domino CMOS Logic

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OffOn
Off
On
VDD VDD
Off
On
VDD
On
11
1 1
0 0
Evaluate
Domino CMOS Logic
On
Off
On
Off
×
VDD VDD
0

52.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 629/21/2020
EMITTER-COUPLED LOGIC (ECL)

53.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 639/21/2020
Differential nature:
1. ↓ noise effect (CMR)
2. Supply current = Const
3. Output levels are referenced to Ground →↑stability.
4. Input-output level compatibility
5. 𝑦 & 𝑦
The Basic Differential Pair

54.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 659/21/2020
-1.32 V
VR is insensitive to ΔVEE
Off Off On
×
L
H
L L
H
L
On OffH
×
A B
A B
VH = -0.88 V
VL = -1.77 V
2
H L
R
V V
V


 outR
outR
Buffer
I Spikes
The ECL Circuit
 freq Cs _MOS Area SI 0.75 @ 1BE CV V I mA  
Emitter Followers

55.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 669/21/2020
Proper Termination
The Emitter-Follower Outputs
RT for matching
VT for proper active biasing of Q3

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-1.32 V
Off Off On
×
VOL =?
4EI mA
-2.07 V
4 mA
-0.98 V
The Voltage Transfer Characteristics
L L
L
H
-0.88 V
-1.77 V
RT

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VIL
100
EI
Off On
-1.32 V
VIL =?
EI
99ER
EA
I
I
  ln 99 115BER BEA TV V V mV   1.435ILV V 
L
L
H
The Voltage Transfer Characteristics
1.205IHV V 

58.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 709/21/2020
 0.88 1.205 0.325H OH IHNM V V V       0 1.435 1.77 0.335L IL LNM V V V      
VIL
100
EI
Off On
-1.32 V
EI
The Noise Margins
L
L
H
The Voltage Transfer Characteristics

59.  Muhammad A M IslamSBE202 Electronic Devices and Circuits 719/21/2020
VIL
100
EI
Off On
-1.32 V
EI
 0.88 1.205 0.325H OH IHNM V V V      
L
L
H
The Noise Margins
The Voltage Transfer Characteristics

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The Voltage Transfer Characteristics

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The Wired-OR Capability
OR

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The Fan-Out
𝐼𝐼𝐿 =
−1.77 + 5.2
50
≅ 69 μA
𝐼𝐼𝐻 =
−0.88 + 5.2
50
+
4
101
≅ 126 μA
𝑑𝑐 𝐹𝑎𝑛 − 𝑂𝑢𝑡 > 90
But ↑Fan-out → ↑C → ↑𝑡 𝑃
𝐹𝑎𝑛 − 𝑂𝑢𝑡 ≅ 10

63.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 759/21/2020
BICMOS DIGITAL CIRCUITS

64.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 769/21/2020
CMOS:
1. ↓ PD
2. ↑ Rin
3. ↑ NM
4. ↓ IO , (for 𝐶𝐿 > 0.5 pF ) → ↑ tP
BJT:
1. ↑ IO → ↓ tP. ECL 2-5 X faster than CMOS
Comparison

65.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 779/21/2020
BiCMOS → high-performance:
1. Digital functions
2. Analog circuits
3. → "system on a chip”.
4. ↑ Complex
5. ↑ Expensive
The BiCMOS Advantages

66.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 789/21/2020
The BiCMOS Inverter

67.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 799/21/2020
The BiCMOS Inverter

68.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 809/21/2020
Totem Pole
The BiCMOS Inverter

69.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 819/21/2020
On
0
Off
Off
On
DD BEV V
↓↓tPLH
The BiCMOS Inverter
Off

70.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 829/21/2020
Off
1
On
On
Off
BEV
↓↓tPHL
The BiCMOS Inverter
Off
↓ VOSwing→↓ NM
OH DD BEV V V 
OL BEV V
No Path to discharge
bases of Q1 & Q2
↑turn off time for Q1 & Q2

71.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 849/21/2020
The BiCMOS Inverter
Off
1
On
On
Off
BEV
R1 & R2 →↓ IB1 & IB2 →↓trs 𝒕 𝒕𝒖𝒓𝒏 𝒐𝒏
0
Off
↑ R(QN&R)→ Slow Pulling Down of Q2
Static PD
Q1 & Q2 turn off faster
Q1 & Q2 Base Discharge

72.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 859/21/2020
On
0
Off
Off
On
Off
On
No Static PD
DD BEV V
The BiCMOS Inverter
Off

73.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 869/21/2020
Off
1
On
On
Off
On
Off
BEV
The BiCMOS Inverter

74.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 879/21/2020
BEV
On
0
Off
Off
On
The BiCMOS Inverter
DDV
Off

75.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 889/21/2020
Off
1
On
On
Off
BEV
The BiCMOS Inverter
Off
DDV0
RCollector & ↑ 𝐶𝐿→Sat
→↓Q turn off time

76.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 899/21/2020
Dynamic Operation
BICMOS speed advantage (over CMOS) iff
driving ↑ fan-out or ↑ CLoad.
CLoad ={50 fF to 100 fF}:
tp_ BICMOS ≈ tp_ CMOS
CLoad =1 pF:
1. tp_ BICMOS = 0.3 ns, &
2. tp_ CMOS =1 ns.

77.  Muhammad A M IslamMTI BIO 313 Electron ic Vision 969/21/2020
BiCMOS Two-Input NAND Logic Gates
PUN
PDN