This document describes the implementation of the Advanced Encryption Standard (AES) algorithm as a custom hardware accelerator connected to a Nios II processor system. AES was written in VHDL and connected to the Nios II system through GPIO pins. This allows AES operations to be controlled through C code in the Nios II IDE while running the AES algorithm in hardware, improving encryption speeds significantly compared to an all-software implementation. Synthesis results showed the hardware AES implementation reduced the number of clock cycles needed for encryption by over 99% compared to running AES solely in software on the Nios II processor.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Dynamic selection of symmetric key cryptographic algorithms for securing data...csandit
Most of the information is in the form of electronic data. A lot of electronic data exchanged
takes place through computer applications. Therefore information exchange through these
applications needs to be secure. Different cryptographic algorithms are usually used to address
these security concerns. However, along with security there are other factors that need to be
considered for practical implementation of different cryptographic algorithms like
implementation cost and performance. This paper provides comparative analysis of time taken
for encryption by seven symmetric key cryptographic algorithms (AES, DES, Triple DES, RC2,
Skipjack, Blowfish and RC4) with variation of parameters like different data types, data density,
data size and key sizes.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Dynamic selection of symmetric key cryptographic algorithms for securing data...csandit
Most of the information is in the form of electronic data. A lot of electronic data exchanged
takes place through computer applications. Therefore information exchange through these
applications needs to be secure. Different cryptographic algorithms are usually used to address
these security concerns. However, along with security there are other factors that need to be
considered for practical implementation of different cryptographic algorithms like
implementation cost and performance. This paper provides comparative analysis of time taken
for encryption by seven symmetric key cryptographic algorithms (AES, DES, Triple DES, RC2,
Skipjack, Blowfish and RC4) with variation of parameters like different data types, data density,
data size and key sizes.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
PREDOMINANCE OF BLOWFISH OVER TRIPLE DATA ENCRYPTION STANDARD SYMMETRIC KEY A...IJNSA Journal
Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.
Advanced Encryption Standard, Multiple Encryption and Triple DES, Block Cipher Modes of
operation, Stream Ciphers and RC4, Confidentiality using Symmetric Encryption, Introduction
to Number Theory: Prime Numbers, Fermat’s and Euler’s Theorems, Testing for Primality, The
Chinese Remainder Theorem, Discrete Logarithms, Public-Key Cryptography and RSA
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are
considering the important performance of these algorithms like CPU time consumption, memory usage and
battery usage. This research tries to demonstrate a fair comparison between the most common algorithms
and with a novel method called Secured Watermark System (SWS) in data encryption field according to
CPU time, packet size and power consumption. It provides a comparison the most known algorithms used
in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of
encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been
conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the
compared encryption algorithms with different parameters.
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
An area and power efficient on chip communication architectures for image enc...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Encryption and Compression of Audio-Video Data Using Enhanced AES and J-Bit A...ijsrd.com
AES is considered a good encryption algorithm in terms of providing security to a network in passing information (data) in form of audio, string, and video and in any other form. However it yields a low throughput resulting in slowness and increasing energy dispensation of server or an application. The Enhanced AES algorithm is proposed in this paper which works by using sequence counters and provides improved throughput as compare to conventional AES algorithm. The J-Bit Encoding is being a compression algorithm in lossless category which doesn't decrease the quality but reduce the size of data to some extent. It has been observed that the proposed encryption algorithm integrated to J-Bit Encoding algorithm will provide the effective security measures as well as increased throughput as a parameter and less bandwidth usage as the actual size of data shall not be sent along the network.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An improved geo encryption algorithm in location based serviceseSAT Journals
Abstract Wireless technology is used in many applications with location based data encryption techniques to secure the communication. The use of knowledge of the mobile user's location called Geo-encryption, produces more secure systems that can be used in different mobile applications. Location Based Data Encryption Methods (LBDEM) is a technique used to enhance the security of such applications called as Location Based Services (LBS). It collects position, time, latitude coordinates and longitude coordinates of mobile nodes and uses for the encryption and decryption process. Geo-encryption plays an important role to raise the security of LBS. Different Geo-protocols have been developed in the same area to add security with better throughput. The Advanced Encryption Standard in Geo-encryption with Dynamic Tolerance Distance (AES-GEDTD) is an approach which gives higher security with a great throughput. This approach mainly uses the AES algorithm, symmetric key encryption algorithm. But applying this algorithm to more complex data like images, videos, etc. like in Digital Film Distribution, we might face the problem of computational overhead. To overcome this problem, we analyze AES and modify it, to reduce the computational overhead. In the modified AES algorithm (M-AES), we omit the calculation of mix column operations and hence the M-AES-GEDTD is a fast and lightweight algorithm for multimedia data. Keywords: Geo-encryption; LBDEM; LBS, Geo-locked Keys .
A combined approach using triple des and blowfish research areaeSAT Journals
Abstract Payment card fraud is causing billions of dollars in losses for the card payment industry. Besides direct losses, the brand name can be affected by loss of consumer confidence due to the fraud. As a result of these growing losses, financial institutions and card issuers are continually seeking new techniques and innovation in payment card fraud detection and prevention. Credit card fraud falls broadly into two categories: behavioral fraud and application fraud. Credit card transactions continue to grow in number, taking an ever-larger share of the US payment system and leading to a higher rate of stolen account numbers and subsequent losses by banks. Improved fraud detection thus has become essential to maintain the viability of the US payment system. Increasingly, the card not present scenario, such as shopping on the internet poses a greater threat as the merchant (the web site) is no longer protected with advantages of physical verification such as signature check, photo identification, etc. In fact, it is almost impossible to perform any of the ‘physical world’ checks necessary to detect who is at the other end of the transaction. This makes the internet extremely attractive to fraud perpetrators. According to a recent survey, the rate at which internet fraud occurs is 20 to25 times higher than ‘physical world’ fraud. However, recent technical developments are showing some promise to check fraud in the card not present scenario. This paper provides an overview of payment card fraud and begins with payment card statistics and the definition of payment card fraud. It also describes various methods used by identity thieves to obtain personal and financial information for the purpose of payment card fraud. In addition, relationship between payment card fraud detection is provided. Finally, some solutions for detecting payment card fraud are also given. Index Terms: Online Frauds, Fraudsters, card fraud, CNP, CVV, AVS
Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASICpaperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
PREDOMINANCE OF BLOWFISH OVER TRIPLE DATA ENCRYPTION STANDARD SYMMETRIC KEY A...IJNSA Journal
Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.
Advanced Encryption Standard, Multiple Encryption and Triple DES, Block Cipher Modes of
operation, Stream Ciphers and RC4, Confidentiality using Symmetric Encryption, Introduction
to Number Theory: Prime Numbers, Fermat’s and Euler’s Theorems, Testing for Primality, The
Chinese Remainder Theorem, Discrete Logarithms, Public-Key Cryptography and RSA
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are
considering the important performance of these algorithms like CPU time consumption, memory usage and
battery usage. This research tries to demonstrate a fair comparison between the most common algorithms
and with a novel method called Secured Watermark System (SWS) in data encryption field according to
CPU time, packet size and power consumption. It provides a comparison the most known algorithms used
in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of
encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been
conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the
compared encryption algorithms with different parameters.
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
An area and power efficient on chip communication architectures for image enc...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Encryption and Compression of Audio-Video Data Using Enhanced AES and J-Bit A...ijsrd.com
AES is considered a good encryption algorithm in terms of providing security to a network in passing information (data) in form of audio, string, and video and in any other form. However it yields a low throughput resulting in slowness and increasing energy dispensation of server or an application. The Enhanced AES algorithm is proposed in this paper which works by using sequence counters and provides improved throughput as compare to conventional AES algorithm. The J-Bit Encoding is being a compression algorithm in lossless category which doesn't decrease the quality but reduce the size of data to some extent. It has been observed that the proposed encryption algorithm integrated to J-Bit Encoding algorithm will provide the effective security measures as well as increased throughput as a parameter and less bandwidth usage as the actual size of data shall not be sent along the network.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An improved geo encryption algorithm in location based serviceseSAT Journals
Abstract Wireless technology is used in many applications with location based data encryption techniques to secure the communication. The use of knowledge of the mobile user's location called Geo-encryption, produces more secure systems that can be used in different mobile applications. Location Based Data Encryption Methods (LBDEM) is a technique used to enhance the security of such applications called as Location Based Services (LBS). It collects position, time, latitude coordinates and longitude coordinates of mobile nodes and uses for the encryption and decryption process. Geo-encryption plays an important role to raise the security of LBS. Different Geo-protocols have been developed in the same area to add security with better throughput. The Advanced Encryption Standard in Geo-encryption with Dynamic Tolerance Distance (AES-GEDTD) is an approach which gives higher security with a great throughput. This approach mainly uses the AES algorithm, symmetric key encryption algorithm. But applying this algorithm to more complex data like images, videos, etc. like in Digital Film Distribution, we might face the problem of computational overhead. To overcome this problem, we analyze AES and modify it, to reduce the computational overhead. In the modified AES algorithm (M-AES), we omit the calculation of mix column operations and hence the M-AES-GEDTD is a fast and lightweight algorithm for multimedia data. Keywords: Geo-encryption; LBDEM; LBS, Geo-locked Keys .
A combined approach using triple des and blowfish research areaeSAT Journals
Abstract Payment card fraud is causing billions of dollars in losses for the card payment industry. Besides direct losses, the brand name can be affected by loss of consumer confidence due to the fraud. As a result of these growing losses, financial institutions and card issuers are continually seeking new techniques and innovation in payment card fraud detection and prevention. Credit card fraud falls broadly into two categories: behavioral fraud and application fraud. Credit card transactions continue to grow in number, taking an ever-larger share of the US payment system and leading to a higher rate of stolen account numbers and subsequent losses by banks. Improved fraud detection thus has become essential to maintain the viability of the US payment system. Increasingly, the card not present scenario, such as shopping on the internet poses a greater threat as the merchant (the web site) is no longer protected with advantages of physical verification such as signature check, photo identification, etc. In fact, it is almost impossible to perform any of the ‘physical world’ checks necessary to detect who is at the other end of the transaction. This makes the internet extremely attractive to fraud perpetrators. According to a recent survey, the rate at which internet fraud occurs is 20 to25 times higher than ‘physical world’ fraud. However, recent technical developments are showing some promise to check fraud in the card not present scenario. This paper provides an overview of payment card fraud and begins with payment card statistics and the definition of payment card fraud. It also describes various methods used by identity thieves to obtain personal and financial information for the purpose of payment card fraud. In addition, relationship between payment card fraud detection is provided. Finally, some solutions for detecting payment card fraud are also given. Index Terms: Online Frauds, Fraudsters, card fraud, CNP, CVV, AVS
Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASICpaperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
Novel Adaptive Hold Logic Circuit for the Multiplier using Add Round Key and ...IJMTST Journal
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The through put of these applications depends on multipliers, if the multipliers are too slow, the performance of entire circuits will be reduced. The negative bias temperature instability effect occurs when a PMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a PMOS transistor and reducing the multiplier speed. Similarly, positive bias temperature instability occurs when an NMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an aging aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A design of a fast parallel pipelined implementation of aes advanced encrypti...ijcsit
The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a
sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is
a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design
of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use
pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on
combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different rounds, while the second is through
parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed
for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in
order to exploit the sources of parallelism in both initial and final round. This enhances the system
performance compared to previous designs. Using two-levels of parallelization benefits from the highly
independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The analysis shows that using
pipeline increases significantly the degree of improvement for both encryption and decryption by
approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column
transformations increases the degree of improvement by approximately 98%. This leads to the conclusion
that the proposed design is scalable and is suitable for real-time applications
Implementation of Cryptography Architecture with High Secure CoreIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
A PERFORMANCE EVALUATION OF COMMON ENCRYPTION TECHNIQUES WITH SECURE WATERMAR...IJNSA Journal
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are considering the important performance of these algorithms like CPU time consumption, memory usage and battery usage. This research tries to demonstrate a fair comparison between the most common algorithms and with a novel method called Secured Watermark System (SWS) in data encryption field according to CPU time, packet size and power consumption. It provides a comparison the most known algorithms used in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the compared encryption algorithms with different parameters.
High throughput FPGA Implementation of Advanced Encryption Standard AlgorithmTELKOMNIKA JOURNAL
The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.
Similar to IMPLEMENTATION OF AES AS A CUSTOM HARDWARE USING NIOS II PROCESSOR (20)
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is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the advancedcomputing. The journal focuses on all technical and practical aspects of high performancecomputing, green computing, pervasive computing, cloud computing etc. The goal of this journalis to bring together researchers anda practitioners from academia and industry to focus onunderstanding advances in computing and establishing new collaborations in these areas
Submit your Research Papers!!!
Advanced Computing: An International Journal ( ACIJ )
ISSN: 2229 -6727 [Online] ; 2229 - 726X [Print]
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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IMPLEMENTATION OF AES AS A CUSTOM HARDWARE USING NIOS II PROCESSOR
1. Advanced Computing: An International Journal ( ACIJ ), Vol.3, No.4, July 2012
DOI : 10.5121/acij.2012.3410 77
IMPLEMENTATION OF AES AS A CUSTOM
HARDWARE USING NIOS II PROCESSOR
Meghana Hasamnis1
and Priyanka Jambhulkar2
and S. S. Limaye3
1
Associate Professor, Department of Electronics Engineering, Shri Ramdeobaba
College of Engineering and Management, Nagpur, India
meghanahasamnis@rediffmail.com
2
Department of Electronics Engineering, Shri Ramdeobaba College of Engineering and
Management, Nagpur, India
priyaj157@gmail.com
3
Professor, Department of Electronics Engineering, Jhulelal Institute of Technology,
Nagpur, India
shyam_limaye@hotmail.com
ABSTRACT
In this paper Advanced Encryption Standard (AES) algorithm has been designed and implemented as
custom hardware. The algorithm is controlled through C-code written in NIOS II IDE. AES as a custom
hardware is interfaced with the system designed around NIOS II Processor using SOPC builder tool. AES
is written in hardware in VHDL language and the interface is through GPIO (General Purpose Input /
Output Port). AES implemented using data size of 128 bits, while the length of the key used is of 128 bits.
The key size of AES used is of 128 bits, as it is secure from the different attacks in existence. The FPGA
used is CYCLONE II from Altera. AES as a custom hardware increases the speed of encryption and
serves as an accelerator and hence improves the performance of the system.
.Keywords
Advanced Encryption Standard (AES), NIOS II Processor, SOPC Builder, NIOS II IDE.
1. INTRODUCTION
Cryptography plays an important role in the security of data. It enables to store sensitive
information or transmit it across insecure networks so that unauthorized persons cannot read it.
Advanced Encryption Standard (AES) is the most common encryption algorithm widely used in
applications such as wireless communication [1]. The Advanced Encryption Standard (AES) is
well known block-cipher algorithm which is easily portable and reasonable security. For secure
exchange of digital data, resulted in large quantities of different encryption algorithms this can
be classified into two groups: Symmetric encryption algorithm (with private key algorithms)
and Asymmetric encryption algorithm (with public key algorithms). Symmetric key algorithms
are in general much faster to execute electronically than asymmetric key algorithms.
The most commonly used symmetric encryption algorithm is AES. The input plain text and the
cipher key are in state array fashion and hence known as a block cipher. The plaintext input are
of fixed size, blocks of 128 bits and produces a block of ciphertext of equal size for each
plaintext block. The most commonly used symmetric encryption algorithms are the data
encryption standard (DES), triple data encryption algorithm (TDEA) and advanced encryption
standard (AES). TDEA has two features which ensure its widespread use over years. First, with
its 168-bit key length, it overcomes the vulnerability to brute-force attack of DEA which has 56-
2. Advanced Computing: An International Journal ( ACIJ ), Vol.3, No.4, July 2012
78
bit key length. Second, the underlying encryption algorithm in TDEA is the same as in DEA.
The main drawback of TDEA is that the algorithm is relatively slow in software. The original
DEA was designed around mid-1970’s suitable for hardware implementation but does not
produce efficient software code. TDEA, which has three times as many as round as DEA, is
correspondingly slower. A secondary drawback is that both DES and TDEA use a 64-bit block
size and hence are prone to attacks [2].
For reasons of both efficiency and security a larger block size is desirable. As a replacement,
NIST in 1997 issued a call for proposals for a new advanced encryption standard (AES),which
should have a security strength equal to or better than TDEA and significantly improved
efficiency. In addition to these general requirements, NIST specified that AES must be a
symmetric block cipher with a block length of 128-bits and support for key lengths of 128,192
and 256 bits.
2. AES ALGORITHM
The AES algorithm is a symmetric-key cipher, in which both the sender and the receiver uses a
single key for encryption and decryption. The length of the plain text is fixed to be 128 bits,
while the key length can be either 128,192, or 256 bits. The key length selected is of 128 bits.
AES algorithm is an iterative algorithm. Every iteration can be called a round, and the total
number of rounds is 10, 12, or 14, when key length is 128, 192, or 256 respectively. The 128 bit
algorithm is divided into 16 bytes. These bytes are represented into 4x4 array called the state
array, and all the different operations of the AES algorithm such as addroundkey, subbytes,
shiftrows, mixcolumns and key expansion are performed on the state [3].
Fig.1 Block Diagram of AES
In AES algorithm encryption of data consists of ten rounds. Each round consists of four
operations or transformations. Only the last round i.e. the tenth round has only three operations
to be performed. The four steps of the algorithm are as below [4].
2.1 SubBytes
Each entry in the state array is of bytes. S-box is a standard substitution table. Every byte in the
state array is substituted by the corresponding byte from the S-box. Each byte of the state array
is changed.
3. Advanced Computing: An International Journal ( ACIJ ), Vol.3, No.4, July 2012
79
2.2 ShiftRows
Each row of the state array is rotated to the left by a specific indent. Second row is shifted by
one position to left, third row by two position and fourth row by three positions to left.
2.3 Mixcolumns
In mixcolumn operation the columns of the State are considered as polynomials over GF (28
)
and are multiplied with a fixed polynomial. The mixcolumn is not used in the last round of the
algorithm.
2.4 Addroundkey
It is a simple bitwise XOR of the current state array block with a portion of expanded key,
expanded by key expansion block.
The flow of AES algorithm is very simple. For encryption, the cipher begins with an
Addroundkey stage, followed by nine rounds. Each round includes all four stages, followed by
tenth round of three stages. Only the Addroundkey stage makes use of key. For this reasons, the
cipher begins and ends with an Addroundkey stage. Any other stage, used at the beginning or at
the end, is reversible without knowing the key and hence would provide no security. The Figure
2 below shows the flow of the encryption algorithm [5].
Fig.2 An AES Encryption Flow Chart
3. SYSTEM DESIGNED USING NIOS II PROCESSOR
A NIOS II is 32 bit soft core processor. A NIOS II processor system consists of a NIOS II
processor, a set of on-chip peripherals, on-chip memory, GPIO’s, all connected with Avalon bus
to generate a system [6, 7]. The Nios II processor is a configurable soft-core processor, as
4. Advanced Computing: An International Journal ( ACIJ ), Vol.3, No.4, July 2012
80
opposed to a fixed, off-the-shelf microcontroller. As Nios II processor is configurable adding
and removing components or features on a system is easy to meets performance goals in terms
of area. Soft-core processor can be targeted to any Altera FPGA family and is not fixed in
silicon [8, 9, 10].
Following are the features of NIOS II processor
• The Nios II processor is a general-purpose RISC processor core, providing:
• Full 32-bit instruction set, data path, and address space
• 32 general-purpose registers
• 32 interrupt sources
• External interrupt controller interface for more interrupt sources
• Access to a variety of on-chip peripherals, and interfaces to off-chip memories and
peripherals
• Single-instruction 32 × 32 multiply and divide producing a 32-bit result
• Optional memory protection unit (MPU)
• Instruction set architecture (ISA) compatible across all Nios II processor systems
• Software development environment based on the GNU C/C++ tool chain and NIOS
IDE
• Performance up to 250 DMIPS
Fig.3 AES connected with NIOS II Processor through GPIO
4. DESIGN STEPS OF AES AS AN ACCELERATOR
The design steps are as follows:
4.1 Integrating the SOPC Builder System into the Quartus II Project
The AES is written in VHDL which is driven as an accelerator /custom hardware and the inputs
and outputs are applied through GPIO in SOPC builder which is given through c-code in IDE.
The contents are as follows
• Standard processor, component cores as a controller part.
• AES is given as hardware written in VHDL.
• Inputs and Outputs are given through GPIO.
Following are the components required in SOPC builder as a controller part of AES
5. Advanced Computing: An International Journal ( ACIJ ), Vol.3, No.4, July 2012
81
Fig.4 System generation using SOPC Builder
4.2 AES program written in hardware is connected with system designed through
General Purpose Input / Output (GPIO)
VHDL program for AES algorithm is written and is connected with the system designed using
the NIOS II processor through GPIO.
4.3 AES Block Diagram File view
Using the Quartus II software, all tasks are performed required to create the final FPGA
hardware design. Using the Quartus II software, pin assignment, locations for I/O signals,
timing requirements are specified, and also other design constraints are applied. Compile the
Quartus II project to produce a .sof file to configure the FPGA.
Fig.5 AES Block Diagram File view
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4.4 Compiled and downloaded in FPGA
Fig. 6 Programmer Window
4.5 Control program written in Nios II IDE
The control part of the AES algorithm is written in C language in NIOS II IDE. The input and
the output is given through C program written in IDE.
4.6 Encrypted result in console window
The inputs and outputs are applied through GPIO in NIOS II IDE which is written in C-code.
• To compile a Nios II project, right click the project in the Nios II C/C++ Projects view,
and click Build Project.
• To run the program on a target board, right click the project in the Nios II C/C++
Projects view, click on Run As, and then click Nios II Hardware.
5. RESULT AND CONCLUSION
5.1 Simulation result of AES used as an accelerator
Fig.7 Encryption results on console window of NIOS II IDE
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5.2 Synthesis Report of AES as an custom hardware
AES is synthesized in Quartus II software and the report is given below
Fig.8 Synthesis Report of AES
5.3 RTL view of AES
AES is synthesized in Quartus II software and the RTL view is given below
Fig.9 RTL view of AES
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Table 1 below shows the CPU clock cycles taken for encryption when AES algorithm is
completely written in software and when AES algorithm written in VHDL and connected with
the system generated using NIOS II processor as a custom hardware.
Table 1. CPU clock cycles for encryption of data
AES algorithm Total time for encryption
(CPU cycles)
Hardware Software
AES 21731020
AES as custom hardware control, inputs and outputs 26425
From the above table 1 number of clock cycles required for AES as custom hardware is very
less as compared to AES in software. Hence AES as custom hardware accelerates the speed of
operation.
REFERENCES
[1] FIPS PUB 197, Advanced Encryption Standard (AES), National Institute of Standards and
Technology, U.S. Department of Commerce, November 2001 (http://csrc.nist.gov/
publications/fips/fips197/fips-197.pdf).
[2] William Stallings “Cryptography and Network Security,” 3rd Edition published by Pearson Education
Inc and Dorling Kindersley Publishing Inc. Advanced Encryption Standard (AES), Nov. 26, 2001.
[3] Stallings W. “Cryptography and Network Security: Principles and Practices, 4th ed., Pearson
Education, Inc. pp. 63-173., 2006.
[4] A. J. Elbirt, W. Yip, B. Chetwynd, and C. Paar., An FPGA implementation and performance
evaluation of theAES block cipher candidate algorithm finalist., presented at Proc. 3rd AES Conf.
(AES3). [Online]. Available: http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
[5] DAEMEN, J.—RIJMEN, V.: AES Proposal: Rijndael, The Rijndael Block Cipher, AES Proposal,
pp.1–45,1999 (http://csrc.nist.gov/CryptoToolkit/aes/)
[6] Altera Corporation, “Quartus II Development Software Handbook v4.0,” [Online Document],2004
February, Available HTTP: http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf
[7] Altera corporation, “Nios Embedded Processor, 32-Bit Programmer’s Reference Manual” [Online
Document] January, 2003
Available:http://www.altera.com/literature/manual/mnl_nios_programmers32.pdf
[8] Rahman T., Pan S. and Zhang Q., “Design of a High Throughput 128-bit (Rijndael
BlockCipher)”,Proceeding of International Multiconferrence of Engineers and computer scientists 2010
Vol II IMECS 2010, March 17- 19,2010, Hongkong.
[9] Nios II Hardware Development Tutorial, altera, December 2009 Altera Corporation Website,
www.altera.com, June 2006
[10] Altera Corporation, “Nios Software Development Tutorial,” [Online Document], 2003 July, [Cited
2004 March 1], Available HTTP: http://www.altera.com/literature/tt/tt_nios_sw.pdf
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Authors
Meghana A. Hasamnis Pursuing Ph.D. from RTM Nagpur University,
Nagpur, India in the field of embedded system. She is M.Tech. from VNIT,
Nagpur, India. She is working as an Associate Professor at Shri. Ramdeobaba
College of Engineering and Management Nagpur, India in the Department of
Electronics Engineering for last 10 years.
Priyanka Jambhulkar Post graduate student in the Department of Electronics
Engineering at Shri. Ramdeobaba College of Engineering and Management,
Nagpur, India, pursuing her M. Tech in VLSI. Done her B.E. in Electronics and
Communication from Nagpur University, India.
Dr. S. S. Limaye Ph.D. from Nagpur University in the faculty of Electronics
Engineering. Currently he is working with JIT as a Principal. He has 38 years of
experience in teaching as well as in industry. He also carried out a number of
consultancy projects at DCM Data products, Delhi, PSI Data Systems
Bangalore, Zen and Art New York. His area of specialization includes digital
signal processing, VLSI design, LDPC codes, Embedded System, CORDIC
algorithm. He is a recognized Supervisor RTM Nagpur University, Nagpur.