This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
Design and Implementation of LNA at 900MHz for GSM applicationsAbdus Sami
This document summarizes the design, simulation, and implementation of a low noise amplifier (LNA) operating at 900MHz for GSM applications. The LNA was designed to have a gain of over 10dB and noise figure of less than 4dB over a 300MHz bandwidth. Simulation results showed a gain of 12dB at the center frequency with variation of ±1.3dB across the bandwidth. The noise figure was 3.9dB. The LNA achieved very high linearity and unconditional stability. The report describes the circuit design, matching network, stability considerations, and hardware implementation through layout generation and component selection.
A Novel Configuration of a Microstrip Microwave Wideband Power Amplifier for ...TELKOMNIKA JOURNAL
RF/microwave power amplifier (PA) is one of the components that has a large effect on the
overall performance of communication system especially in transmitter system and their design is decided
by the parameters of transistor selected. This letter presents a new concept of a wide-band microwave
amplifier using scattering parameters that is often used in the radio frequency communication systemas an
application of the active integrated antenna[1- 2]. This power amplifier operates from 1.75 GHz to 2.15GHz
frequency and it is based on AT-41410 NPN transistor that has a high transition frequency of 10GHz. The
proposed Single Stage PA is designed by microstrip technology and simulated with Advanced Design
System (ADS) software. The simulation results indicate good performances; the small power gain (S21) is
changed between 11.8 and 10dB. For the input reflection coefficient (S11) is varied between -11 and -
22.5dB. Regarding the output reflection coefficient (S22) is varied between -13.1 and -18.7dB over the
wide frequency band of 1.75-2.15GHz and stability without oscillating over a wide range of frequencies.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
This document describes the design of a 2.4GHz CMOS power amplifier for wireless communication using a 130nm technology. It begins with an introduction to power amplifiers and their importance in wireless transmitters for amplifying transmitted signals. It then reviews previous work on power amplifier design using different technologies. The document proposes a class-B power amplifier design using a 130nm technology to achieve a gain of more than 15dB. Simulation results show the designed class-B power amplifier meets the frequency response requirement at 2.4GHz with a gain of 67.321dB. The power amplifier is designed to operate with a power supply voltage range of 1.3-3V, making it suitable for battery-powered portable electronics and wireless communication
The document summarizes the design of a low noise amplifier meeting specific gain, noise figure, return loss, and stability specifications. The amplifier was designed using a bipolar junction transistor with input and output matching networks composed of lumped elements. Simulation results showed the design met or nearly met all specifications except output return loss. Fabricated measurements matched simulations but did not fully meet specifications, potentially due to fabrication and component imperfections. Overall the amplifier performed well but could be improved with a higher bias point design.
A Review on Wide Bandwidth Low Noise Amplifier for Modern Wireless CommunicationIRJET Journal
This document reviews techniques for designing wide bandwidth low noise amplifiers for modern wireless communication. It discusses several techniques used in recent decades to improve the performance and linearity of low noise amplifiers, including wide range derivative superposition technique, direct-coupled amplifier topology, resistive shunt feedback topology, forward combining technique, and gate-inductive gain-peaking technique. The document also reviews the applications of low noise amplifiers in areas like low noise amplifier, distributed amplifier, broadband mixer, power amplifier and active balunes.
A novel cmos model design for 2 6 g hz wideband lna input matching using resi...IAEME Publication
This document describes a novel CMOS model design for a 2-6 GHz wideband low noise amplifier (LNA) input matching using resistive feedback topology for WiMAX applications. The proposed LNA uses a two-stage resistive shunt feedback structure with a simplified band pass filter to provide wide input impedance matching over 2-6 GHz. Simulation results show the LNA achieves a maximum gain of 16.5 dB, minimum noise figure of 4.2 dB, and input return loss of -12 dB across the band. The power consumption is 15 mW. A performance comparison with other published LNA designs demonstrates that this LNA is suitable for wideband applications like WiMAX.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
Design and Implementation of LNA at 900MHz for GSM applicationsAbdus Sami
This document summarizes the design, simulation, and implementation of a low noise amplifier (LNA) operating at 900MHz for GSM applications. The LNA was designed to have a gain of over 10dB and noise figure of less than 4dB over a 300MHz bandwidth. Simulation results showed a gain of 12dB at the center frequency with variation of ±1.3dB across the bandwidth. The noise figure was 3.9dB. The LNA achieved very high linearity and unconditional stability. The report describes the circuit design, matching network, stability considerations, and hardware implementation through layout generation and component selection.
A Novel Configuration of a Microstrip Microwave Wideband Power Amplifier for ...TELKOMNIKA JOURNAL
RF/microwave power amplifier (PA) is one of the components that has a large effect on the
overall performance of communication system especially in transmitter system and their design is decided
by the parameters of transistor selected. This letter presents a new concept of a wide-band microwave
amplifier using scattering parameters that is often used in the radio frequency communication systemas an
application of the active integrated antenna[1- 2]. This power amplifier operates from 1.75 GHz to 2.15GHz
frequency and it is based on AT-41410 NPN transistor that has a high transition frequency of 10GHz. The
proposed Single Stage PA is designed by microstrip technology and simulated with Advanced Design
System (ADS) software. The simulation results indicate good performances; the small power gain (S21) is
changed between 11.8 and 10dB. For the input reflection coefficient (S11) is varied between -11 and -
22.5dB. Regarding the output reflection coefficient (S22) is varied between -13.1 and -18.7dB over the
wide frequency band of 1.75-2.15GHz and stability without oscillating over a wide range of frequencies.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
This document describes the design of a 2.4GHz CMOS power amplifier for wireless communication using a 130nm technology. It begins with an introduction to power amplifiers and their importance in wireless transmitters for amplifying transmitted signals. It then reviews previous work on power amplifier design using different technologies. The document proposes a class-B power amplifier design using a 130nm technology to achieve a gain of more than 15dB. Simulation results show the designed class-B power amplifier meets the frequency response requirement at 2.4GHz with a gain of 67.321dB. The power amplifier is designed to operate with a power supply voltage range of 1.3-3V, making it suitable for battery-powered portable electronics and wireless communication
The document summarizes the design of a low noise amplifier meeting specific gain, noise figure, return loss, and stability specifications. The amplifier was designed using a bipolar junction transistor with input and output matching networks composed of lumped elements. Simulation results showed the design met or nearly met all specifications except output return loss. Fabricated measurements matched simulations but did not fully meet specifications, potentially due to fabrication and component imperfections. Overall the amplifier performed well but could be improved with a higher bias point design.
A Review on Wide Bandwidth Low Noise Amplifier for Modern Wireless CommunicationIRJET Journal
This document reviews techniques for designing wide bandwidth low noise amplifiers for modern wireless communication. It discusses several techniques used in recent decades to improve the performance and linearity of low noise amplifiers, including wide range derivative superposition technique, direct-coupled amplifier topology, resistive shunt feedback topology, forward combining technique, and gate-inductive gain-peaking technique. The document also reviews the applications of low noise amplifiers in areas like low noise amplifier, distributed amplifier, broadband mixer, power amplifier and active balunes.
A novel cmos model design for 2 6 g hz wideband lna input matching using resi...IAEME Publication
This document describes a novel CMOS model design for a 2-6 GHz wideband low noise amplifier (LNA) input matching using resistive feedback topology for WiMAX applications. The proposed LNA uses a two-stage resistive shunt feedback structure with a simplified band pass filter to provide wide input impedance matching over 2-6 GHz. Simulation results show the LNA achieves a maximum gain of 16.5 dB, minimum noise figure of 4.2 dB, and input return loss of -12 dB across the band. The power consumption is 15 mW. A performance comparison with other published LNA designs demonstrates that this LNA is suitable for wideband applications like WiMAX.
Low Noise Amplifier at 2 GHz using the transistor NE85639 in ADSKarthik Rathinavel
• Systematically designed a LNA and its biasing using non-ideal components such as Microstrip TLs resistors, capacitors etc.
• Calculated the S parameters of the Transistor and simulated the gain and bandwidth to be 10 dB and 1 GHz respectively.
• Achieved a Noise Figure of 3.2 dB and s11 of -20 dB in the final design.
The document discusses the design and implementation of a P-band RF low noise amplifier (LNA). It begins with an introduction to LNAs, explaining that their main function is to amplify weak signals while introducing minimal noise. It then discusses the use of pseudomorphic high electron mobility transistors (pHEMTs) for LNA design due to their ability to provide high gain and low noise figure. The document outlines the objectives and methodology for the project, which is to design an LNA with specifications including a frequency range of 50MHz-1GHz, gain of at least 22dB, noise figure below 4dB and input/output impedance of 50 ohms. It provides background on relevant LNA design concepts and
This document describes the design, implementation, and simulation of a 2-GHz low noise amplifier (LNA). The LNA is designed using both lumped elements and distributed elements approaches. Key steps in the design process are discussed, including the use of the MESFET transistor, input and output matching networks, and performance analysis using the Smith Chart. The LNA provides a noise figure of 0.358 dB, gain of 16.778 dB, and meets other specifications. Simulation results show that the lumped elements approach achieves better performance than the distributed elements approach. The document outlines the design process and evaluation of LNAs to meet requirements for wireless communication systems.
Design of LED Driver Power Based on LNK417EGIOSRJEEE
In recent years, people have been committed to the development and the design of new lighting sources. The life of LED lamps depends on the life of the LED driver which has a great relationship with the life of the electrolytic capacitor. In this paper the advantages of the drive power of the electrolytic capacitor are analyzed and the design of the PFC circuit and the transformer is described in details. On the basis of the LNK417 driver chip, a novel single-stage flyback drive circuit without the electrolytic capacitor is designed, which combines the power factor correction technology and constant current control to avoid the use of large electrolytic capacitors. The design and implementation of the control circuit are given and the overall performance is tested and analyzed in the article. The test results show that the driver is of high efficiency, high PF and long life etc. The efficiency is up to 85% and the PF value is not less than 0.9.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
This document describes the design of a 2.4 GHz CMOS low noise amplifier (LNA) using a resistive feedback topology in 0.13μm technology. A series inductor input matching network is used to provide input matching. Simulation results show the LNA has a voltage gain (S21) of 28dB, noise figure of 2.2dB, input return loss (S11) of -10.7dB, third order intercept point (IIP3) of -22.4dBm, while consuming 4.8mW of power from a 1.2V supply. The resistive feedback topology improves performance over other designs by increasing gain and reducing the chip area required.
This document summarizes the analysis and design of a variable gain amplifier using FinFET technology. It finds that FinFETs have several advantages over planar MOSFETs for analog applications, including reduced power dissipation and better voltage gain without degradation of noise or linearity. This makes FinFETs attractive for low-frequency RF applications around 5 GHz. Simulation results show that a variable gain amplifier designed using FinFETs has lower power dissipation and an improved gain range compared to one designed with MOSFETs. However, FinFETs have higher parasitic resistance, which degrades performance at high frequencies where MOSFETs maintain an advantage.
This document provides a laboratory manual for experiments in a Microwave and Digital Communication lab. It includes 12 experiments covering topics like the characteristics of reflex klystron tubes, Gunn diodes, directional couplers, standing wave ratio measurements, and digital modulation techniques including time division multiplexing, frequency shift keying, phase shift keying, and differential phase shift keying. The manual provides the objectives, theoretical background, experimental procedures, observations tables and questions for each experiment.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
An Ultra-Low Voltage, Wideband Low Noise Amplifier Design TechniqueIRJET Journal
This document describes the design of an ultra-low voltage, wideband low noise amplifier (LNA) using current reuse techniques. The LNA is a critical component in radio receivers that must provide gain while maintaining low noise figure and power consumption. The proposed LNA design uses current reuse and inductive peaking to achieve high performance metrics like gain and noise figure while keeping power dissipation low. Simulation results show the LNA has an input noise of a few microvolts, output noise of nanovolts, power dissipation of 26.854 nanowatts, and input and output return losses below -10 dB, demonstrating good matching across its operating bandwidth.
Bridgeless CUK Rectifier with Output Voltage Regulation using Fuzzy controllerIOSR Journals
This document describes a bridgeless CUK rectifier for power factor correction with output voltage regulation using a fuzzy controller. The bridgeless CUK rectifier lacks an input diode bridge to reduce conduction losses. It is operated in discontinuous conduction mode for near unity power factor and zero voltage switching. Simulation results show the input current tracks the voltage with a power factor of 0.998 and total harmonic distortion of 2%. A fuzzy logic controller is used to regulate the output voltage to a reference value of 40V and maintains the voltage even with changes in input voltage or load.
DESIGN OF HIGH EFFICIENCY TWO STAGE POWER AMPLIFIER IN 0.13UM RF CMOS TECHNOL...VLSICS Design
This two-stage power amplifier was designed in 0.13um RF CMOS technology for 2.4GHz WLAN applications. It consists of a driver stage using a cascode topology and a power stage using a basic topology. At 1dB compression, it delivers 20.028dBm of output power with 44.669% power added efficiency. Maximum output power is 22.002dBm with 70.196% efficiency. Input and output return losses are -11.132dB and -12.467dB respectively, with a gain of 43.745dB at 1dB compression.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This document summarizes the design of a 2.4 GHz class E power amplifier and RF switch for healthcare applications. The power amplifier was designed using Cadence software with a 0.18um CMOS process and can output 16dBm of power. The RF switch was designed using Cadence with a 180nm SOI process. Simulation results showed the power amplifier had over 50dB of gain and the S11 was below -10dB. The RF switch had over 1.36dB of insertion loss and 58.5dB of isolation at 5GHz. Both the power amplifier and RF switch met the design requirements for wireless sensor networks for healthcare applications.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
Temperature analysis of lna with improved linearity for rf receivereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Temperature analysis of lna with improved linearity for rf receivereSAT Journals
Abstract In this paper we are fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. It developed using cascode amplifier with inductors. RC linearization circuit is designed to improve the linearity of the design. Cascode LNA circuit is designed for linearity improvement. In this work Temperature analysis is carried out for LNA circuit performance improvement fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, good temperature stability is achieved. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, we are able to achieve good temperature stability. The Low Noise Amplifier is a special type of electronic amplifier used in communication systems which amplifies very weak signals captured by an antenna. Keywords: Linearity improvement LNA circuit, DSCH and Microwind software.
BPSK Modulation and Demodulation with Power Line Carrier Communication and GS...IAES-IJPEDS
GSM/GPRS and PLC communication are used for Automatic Meter Reading
(AMR) applications. These AMR systems have made substantial progress
over the recent years in terms of functionality, scalability, performance
and openness such that they can perform remote metering applications for
very demanding and complex systems. By using BPSK (Binary Phase Shift
Keying) modulation with Power Line Carrier Communication, Smart
Metering can be done in Rural Smart Micro-grids. The design
and Simulation of BPSK Modulation and Demodulation are successfully
done by using MATLAB/Simulink software. The advantages of using BPSK
modulation over the QPSK modulation and the advantages of PLC
Communication over the GSM Communication is identified in this paper.
1) The document describes the design and simulation of a linear amplifier that operates in the C band frequency range of 5-6 GHz.
2) A Class A amplifier design approach was used to ensure linearity at higher frequencies. A GaAs FET transistor was selected and biased in its linear region.
3) Input and output matching networks were designed using S-parameter simulations. Multiple transistor stages were cascaded to increase the gain to 30 dB.
4) Simulation results showed a gain of 19.241 dB, S-parameters, stability above 1, and a noise figure of around 3 dB as expected for a low noise pre-amplifier.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
This document describes the design of a low noise amplifier (LNA) for wireless applications operating at 900 MHz. The LNA was implemented using a 0.13um RF CMOS technology and a cascode topology with inductive source degeneration. Simulation results showed the LNA has a gain of 26 dB, noise figure of 1.04 dB, input return loss of -14 dB, output return loss of -6.55 dB, reverse isolation of -39.76 dB, and power consumption of 115uW from a 2.5V supply. The LNA meets the requirements of low noise figure, high gain and low power consumption for a 900 MHz wireless application.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
Low Noise Amplifier at 2 GHz using the transistor NE85639 in ADSKarthik Rathinavel
• Systematically designed a LNA and its biasing using non-ideal components such as Microstrip TLs resistors, capacitors etc.
• Calculated the S parameters of the Transistor and simulated the gain and bandwidth to be 10 dB and 1 GHz respectively.
• Achieved a Noise Figure of 3.2 dB and s11 of -20 dB in the final design.
The document discusses the design and implementation of a P-band RF low noise amplifier (LNA). It begins with an introduction to LNAs, explaining that their main function is to amplify weak signals while introducing minimal noise. It then discusses the use of pseudomorphic high electron mobility transistors (pHEMTs) for LNA design due to their ability to provide high gain and low noise figure. The document outlines the objectives and methodology for the project, which is to design an LNA with specifications including a frequency range of 50MHz-1GHz, gain of at least 22dB, noise figure below 4dB and input/output impedance of 50 ohms. It provides background on relevant LNA design concepts and
This document describes the design, implementation, and simulation of a 2-GHz low noise amplifier (LNA). The LNA is designed using both lumped elements and distributed elements approaches. Key steps in the design process are discussed, including the use of the MESFET transistor, input and output matching networks, and performance analysis using the Smith Chart. The LNA provides a noise figure of 0.358 dB, gain of 16.778 dB, and meets other specifications. Simulation results show that the lumped elements approach achieves better performance than the distributed elements approach. The document outlines the design process and evaluation of LNAs to meet requirements for wireless communication systems.
Design of LED Driver Power Based on LNK417EGIOSRJEEE
In recent years, people have been committed to the development and the design of new lighting sources. The life of LED lamps depends on the life of the LED driver which has a great relationship with the life of the electrolytic capacitor. In this paper the advantages of the drive power of the electrolytic capacitor are analyzed and the design of the PFC circuit and the transformer is described in details. On the basis of the LNK417 driver chip, a novel single-stage flyback drive circuit without the electrolytic capacitor is designed, which combines the power factor correction technology and constant current control to avoid the use of large electrolytic capacitors. The design and implementation of the control circuit are given and the overall performance is tested and analyzed in the article. The test results show that the driver is of high efficiency, high PF and long life etc. The efficiency is up to 85% and the PF value is not less than 0.9.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
This document describes the design of a 2.4 GHz CMOS low noise amplifier (LNA) using a resistive feedback topology in 0.13μm technology. A series inductor input matching network is used to provide input matching. Simulation results show the LNA has a voltage gain (S21) of 28dB, noise figure of 2.2dB, input return loss (S11) of -10.7dB, third order intercept point (IIP3) of -22.4dBm, while consuming 4.8mW of power from a 1.2V supply. The resistive feedback topology improves performance over other designs by increasing gain and reducing the chip area required.
This document summarizes the analysis and design of a variable gain amplifier using FinFET technology. It finds that FinFETs have several advantages over planar MOSFETs for analog applications, including reduced power dissipation and better voltage gain without degradation of noise or linearity. This makes FinFETs attractive for low-frequency RF applications around 5 GHz. Simulation results show that a variable gain amplifier designed using FinFETs has lower power dissipation and an improved gain range compared to one designed with MOSFETs. However, FinFETs have higher parasitic resistance, which degrades performance at high frequencies where MOSFETs maintain an advantage.
This document provides a laboratory manual for experiments in a Microwave and Digital Communication lab. It includes 12 experiments covering topics like the characteristics of reflex klystron tubes, Gunn diodes, directional couplers, standing wave ratio measurements, and digital modulation techniques including time division multiplexing, frequency shift keying, phase shift keying, and differential phase shift keying. The manual provides the objectives, theoretical background, experimental procedures, observations tables and questions for each experiment.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
An Ultra-Low Voltage, Wideband Low Noise Amplifier Design TechniqueIRJET Journal
This document describes the design of an ultra-low voltage, wideband low noise amplifier (LNA) using current reuse techniques. The LNA is a critical component in radio receivers that must provide gain while maintaining low noise figure and power consumption. The proposed LNA design uses current reuse and inductive peaking to achieve high performance metrics like gain and noise figure while keeping power dissipation low. Simulation results show the LNA has an input noise of a few microvolts, output noise of nanovolts, power dissipation of 26.854 nanowatts, and input and output return losses below -10 dB, demonstrating good matching across its operating bandwidth.
Bridgeless CUK Rectifier with Output Voltage Regulation using Fuzzy controllerIOSR Journals
This document describes a bridgeless CUK rectifier for power factor correction with output voltage regulation using a fuzzy controller. The bridgeless CUK rectifier lacks an input diode bridge to reduce conduction losses. It is operated in discontinuous conduction mode for near unity power factor and zero voltage switching. Simulation results show the input current tracks the voltage with a power factor of 0.998 and total harmonic distortion of 2%. A fuzzy logic controller is used to regulate the output voltage to a reference value of 40V and maintains the voltage even with changes in input voltage or load.
DESIGN OF HIGH EFFICIENCY TWO STAGE POWER AMPLIFIER IN 0.13UM RF CMOS TECHNOL...VLSICS Design
This two-stage power amplifier was designed in 0.13um RF CMOS technology for 2.4GHz WLAN applications. It consists of a driver stage using a cascode topology and a power stage using a basic topology. At 1dB compression, it delivers 20.028dBm of output power with 44.669% power added efficiency. Maximum output power is 22.002dBm with 70.196% efficiency. Input and output return losses are -11.132dB and -12.467dB respectively, with a gain of 43.745dB at 1dB compression.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This document summarizes the design of a 2.4 GHz class E power amplifier and RF switch for healthcare applications. The power amplifier was designed using Cadence software with a 0.18um CMOS process and can output 16dBm of power. The RF switch was designed using Cadence with a 180nm SOI process. Simulation results showed the power amplifier had over 50dB of gain and the S11 was below -10dB. The RF switch had over 1.36dB of insertion loss and 58.5dB of isolation at 5GHz. Both the power amplifier and RF switch met the design requirements for wireless sensor networks for healthcare applications.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
Temperature analysis of lna with improved linearity for rf receivereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Temperature analysis of lna with improved linearity for rf receivereSAT Journals
Abstract In this paper we are fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. It developed using cascode amplifier with inductors. RC linearization circuit is designed to improve the linearity of the design. Cascode LNA circuit is designed for linearity improvement. In this work Temperature analysis is carried out for LNA circuit performance improvement fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, good temperature stability is achieved. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, we are able to achieve good temperature stability. The Low Noise Amplifier is a special type of electronic amplifier used in communication systems which amplifies very weak signals captured by an antenna. Keywords: Linearity improvement LNA circuit, DSCH and Microwind software.
BPSK Modulation and Demodulation with Power Line Carrier Communication and GS...IAES-IJPEDS
GSM/GPRS and PLC communication are used for Automatic Meter Reading
(AMR) applications. These AMR systems have made substantial progress
over the recent years in terms of functionality, scalability, performance
and openness such that they can perform remote metering applications for
very demanding and complex systems. By using BPSK (Binary Phase Shift
Keying) modulation with Power Line Carrier Communication, Smart
Metering can be done in Rural Smart Micro-grids. The design
and Simulation of BPSK Modulation and Demodulation are successfully
done by using MATLAB/Simulink software. The advantages of using BPSK
modulation over the QPSK modulation and the advantages of PLC
Communication over the GSM Communication is identified in this paper.
1) The document describes the design and simulation of a linear amplifier that operates in the C band frequency range of 5-6 GHz.
2) A Class A amplifier design approach was used to ensure linearity at higher frequencies. A GaAs FET transistor was selected and biased in its linear region.
3) Input and output matching networks were designed using S-parameter simulations. Multiple transistor stages were cascaded to increase the gain to 30 dB.
4) Simulation results showed a gain of 19.241 dB, S-parameters, stability above 1, and a noise figure of around 3 dB as expected for a low noise pre-amplifier.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
This document describes the design of a low noise amplifier (LNA) for wireless applications operating at 900 MHz. The LNA was implemented using a 0.13um RF CMOS technology and a cascode topology with inductive source degeneration. Simulation results showed the LNA has a gain of 26 dB, noise figure of 1.04 dB, input return loss of -14 dB, output return loss of -6.55 dB, reverse isolation of -39.76 dB, and power consumption of 115uW from a 2.5V supply. The LNA meets the requirements of low noise figure, high gain and low power consumption for a 900 MHz wireless application.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
Negative image amplifier technique for performance enhancement of ultra wideb...IJECEIAES
The paper aims at designing of two stage cascaded ultra-wideband (UWB) low noise amplifier (LNA) by using negative image amplifier technique. The objective of this article is to show the performance improvement using negative image amplifier technique and realization of negative valued lumped elements into microstrip line geometry. The innovative technique to realize the negative lumped elements are carried out by using Richard’s Transformation and transmission line calculation. The AWR microwave office tool is used to obtain characteristics of UWB LNA design with hybrid microwave integrated circuit (HMIC) technology. The 2-stage cascaded LNA design using negative image amplifier technique achieves average gain of 23dB gain and low noise figure of less than 2dB with return loss less than -8dB for UWB 3-10GHz. The Proper bias circuit is extracted using DC characteristics of transistor at biasing point 2V, 20mA and discussed in detail with LNA layout. The negative image matching technique is applied for both input and output matching network. This work will be useful for all low power UWB wireless receiver applications.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
This document summarizes the design of a low noise amplifier (LNA) operating at 2.45GHz. The LNA uses a cascode topology with inductive source degeneration implemented in a 120nm CMOS process. Simulation results show the LNA meets specifications for gain, return loss, output match, noise figure, and linearity over 2.4-2.5GHz. Variability analysis demonstrates performance remains within specifications with +/-10% parameter variations. The compact layout achieves good matching through careful device placement and use of appropriate passive components to minimize parasitics.
A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias techniqueTELKOMNIKA JOURNAL
This document describes a 28 GHz power amplifier (PA) designed using a 0.18 μm CMOS process. The PA uses a cascade configuration with three stages to achieve high power gain. The input stage employs reverse body biasing to reduce power consumption. Simulation results show the PA achieves a power gain of 9.51 dB, saturated output power of 11.10 dBm, and maximum power added efficiency of 16.55% while consuming only 32.03 mW of power. Compared to a design without reverse body biasing, the proposed PA has 16.55% power added efficiency, lower power consumption of 32.03 mW, and higher power gain of 9.51 dB. This PA is suitable for 5G
A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifi...journalBEEI
A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
Design and Implementation of a Low Noise Amplifier for Ultra Wideband Applica...IOSRJVSP
This paper represents the design and implementation of Low Noise Amplifier for Ultra wideband application using 0.18μm CMOS Technology. The proposed two stage LNA is for a 3-5 GHz. At supply voltage of 1.8V, for the exceed limit of 50μm of width of each transistor, the power consumption is 7.22mW. Noise figure is 4.33dB, Maximum power gain i.e. S21 is 20.4dB, S12 < -20dB, S11 < -8dB, S22 < -10dB. For the required bandwidth range, LNA is unconditionally stable and have good linearity
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Design of Low Noise Amplifier for Wimax ApplicationIOSR Journals
The document describes the design of a low noise amplifier (LNA) for WiMAX applications operating in the 3.3-3.8 GHz range. It discusses testing the transistor to check for stability and gain. Input and output matching is performed using stub matching networks to achieve low noise figure and high gain. A passive biasing circuit is designed using resistors and capacitors. Two LNA techniques, feedback amplifier and balanced amplifier, are simulated to find the best performance; the feedback amplifier provides a nominal noise figure of 1.02 dB and gain of 12 dB.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
The document describes a low power, low phase noise CMOS LC oscillator designed and simulated using a 180nm CMOS technology. Key results include:
1) The oscillator achieves a phase noise of -96 dBc/Hz at 1MHz with a tuning range of 4.8-8.3 GHz by varying the control voltage from 0-2V.
2) It consumes 3.8mW of power at an output power of -8.92dBm.
3) Simulation results show the tuning range, output waveform, and phase noise performance meet design goals for a low power VCO for wireless applications like 5G.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
This document reviews the design and performance analysis of low power transceiver circuits in wireless sensor networks. It discusses the key components of transceivers including power amplifiers and mixers. For power amplifiers, CMOS implementations are highlighted as offering advantages over other technologies like lower power dissipation, smaller size, and lower cost. The document also reviews several existing studies on power amplifiers and mixers designed for wireless applications. It proposes a two-stage CMOS power amplifier design and discusses improving power added efficiency while maintaining output power. Overall, the document analyzes the importance of low power transceiver circuits for wireless sensor networks and reviews relevant existing work.
Review on Design and Performance Analysis of Low Power Transceiver Circuit in...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired.
Low Power SI Class E Power Amplifier and Rf Switch for Health Careieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software. And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired
Dickson voltage multiplier with 1 to 6 stages for dual-band rectifiers (2.45/...TELKOMNIKA JOURNAL
This paper presents the design of highly efficient rectifiers that can operate at WiFi frequencies (2.45 GHz and 5.8 GHz) and match low input power. The designed dual-band rectifiers use multi-stage dickson voltage multipliers (DVM) (from 1 to 6 stages), and the main idea of this paper is to find the number of stages that offers the best performance and that can be used by applications that operate within the same constraints (operating frequencies, input power). The efficiency and the output voltage (Vout) are the parameters studied to analyze the designed rectifiers. The results showed that as the number of DVM stages increased, the efficiency curves for both frequencies shifted to the higher input power range, even when using the same diode (SMS7630) and the same load (5 KΩ). We concluded that the rectifier with 1-stage DVM is the most suitable to be used for low input power at the selected frequencies since it provides an efficiency of 57.734% at 0 dBm for 2.45 GHz and 36.225% at 1 dBm of input power for 5.8 GHz.
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
Similar to Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology (20)
Square transposition: an approach to the transposition process in block cipherjournalBEEI
The transposition process is needed in cryptography to create a diffusion effect on data encryption standard (DES) and advanced encryption standard (AES) algorithms as standard information security algorithms by the National Institute of Standards and Technology. The problem with DES and AES algorithms is that their transposition index values form patterns and do not form random values. This condition will certainly make it easier for a cryptanalyst to look for a relationship between ciphertexts because some processes are predictable. This research designs a transposition algorithm called square transposition. Each process uses square 8 × 8 as a place to insert and retrieve 64-bits. The determination of the pairing of the input scheme and the retrieval scheme that have unequal flow is an important factor in producing a good transposition. The square transposition can generate random and non-pattern indices so that transposition can be done better than DES and AES.
Hyper-parameter optimization of convolutional neural network based on particl...journalBEEI
The document proposes using a particle swarm optimization (PSO) algorithm to optimize the hyperparameters of a convolutional neural network (CNN) for image classification. The PSO algorithm is used to find optimal values for CNN hyperparameters like the number and size of convolutional filters. In experiments on the MNIST handwritten digit dataset, the optimized CNN achieved a testing error rate of 0.87%, which is competitive with state-of-the-art models. The proposed approach finds optimized CNN architectures automatically without requiring manual design or encoding strategies during training.
Supervised machine learning based liver disease prediction approach with LASS...journalBEEI
In this contemporary era, the uses of machine learning techniques are increasing rapidly in the field of medical science for detecting various diseases such as liver disease (LD). Around the globe, a large number of people die because of this deadly disease. By diagnosing the disease in a primary stage, early treatment can be helpful to cure the patient. In this research paper, a method is proposed to diagnose the LD using supervised machine learning classification algorithms, namely logistic regression, decision tree, random forest, AdaBoost, KNN, linear discriminant analysis, gradient boosting and support vector machine (SVM). We also deployed a least absolute shrinkage and selection operator (LASSO) feature selection technique on our taken dataset to suggest the most highly correlated attributes of LD. The predictions with 10 fold cross-validation (CV) made by the algorithms are tested in terms of accuracy, sensitivity, precision and f1-score values to forecast the disease. It is observed that the decision tree algorithm has the best performance score where accuracy, precision, sensitivity and f1-score values are 94.295%, 92%, 99% and 96% respectively with the inclusion of LASSO. Furthermore, a comparison with recent studies is shown to prove the significance of the proposed system.
A secure and energy saving protocol for wireless sensor networksjournalBEEI
The research domain for wireless sensor networks (WSN) has been extensively conducted due to innovative technologies and research directions that have come up addressing the usability of WSN under various schemes. This domain permits dependable tracking of a diversity of environments for both military and civil applications. The key management mechanism is a primary protocol for keeping the privacy and confidentiality of the data transmitted among different sensor nodes in WSNs. Since node's size is small; they are intrinsically limited by inadequate resources such as battery life-time and memory capacity. The proposed secure and energy saving protocol (SESP) for wireless sensor networks) has a significant impact on the overall network life-time and energy dissipation. To encrypt sent messsages, the SESP uses the public-key cryptography’s concept. It depends on sensor nodes' identities (IDs) to prevent the messages repeated; making security goals- authentication, confidentiality, integrity, availability, and freshness to be achieved. Finally, simulation results show that the proposed approach produced better energy consumption and network life-time compared to LEACH protocol; sensors are dead after 900 rounds in the proposed SESP protocol. While, in the low-energy adaptive clustering hierarchy (LEACH) scheme, the sensors are dead after 750 rounds.
Plant leaf identification system using convolutional neural networkjournalBEEI
This paper proposes a leaf identification system using convolutional neural network (CNN). This proposed system can identify five types of local Malaysia leaf which were acacia, papaya, cherry, mango and rambutan. By using CNN from deep learning, the network is trained from the database that acquired from leaf images captured by mobile phone for image classification. ResNet-50 was the architecture has been used for neural networks image classification and training the network for leaf identification. The recognition of photographs leaves requested several numbers of steps, starting with image pre-processing, feature extraction, plant identification, matching and testing, and finally extracting the results achieved in MATLAB. Testing sets of the system consists of 3 types of images which were white background, and noise added and random background images. Finally, interfaces for the leaf identification system have developed as the end software product using MATLAB app designer. As a result, the accuracy achieved for each training sets on five leaf classes are recorded above 98%, thus recognition process was successfully implemented.
Customized moodle-based learning management system for socially disadvantaged...journalBEEI
This study aims to develop Moodle-based LMS with customized learning content and modified user interface to facilitate pedagogical processes during covid-19 pandemic and investigate how teachers of socially disadvantaged schools perceived usability and technology acceptance. Co-design process was conducted with two activities: 1) need assessment phase using an online survey and interview session with the teachers and 2) the development phase of the LMS. The system was evaluated by 30 teachers from socially disadvantaged schools for relevance to their distance learning activities. We employed computer software usability questionnaire (CSUQ) to measure perceived usability and the technology acceptance model (TAM) with insertion of 3 original variables (i.e., perceived usefulness, perceived ease of use, and intention to use) and 5 external variables (i.e., attitude toward the system, perceived interaction, self-efficacy, user interface design, and course design). The average CSUQ rating exceeded 5.0 of 7 point-scale, indicated that teachers agreed that the information quality, interaction quality, and user interface quality were clear and easy to understand. TAM results concluded that the LMS design was judged to be usable, interactive, and well-developed. Teachers reported an effective user interface that allows effective teaching operations and lead to the system adoption in immediate time.
Understanding the role of individual learner in adaptive and personalized e-l...journalBEEI
Dynamic learning environment has emerged as a powerful platform in a modern e-learning system. The learning situation that constantly changing has forced the learning platform to adapt and personalize its learning resources for students. Evidence suggested that adaptation and personalization of e-learning systems (APLS) can be achieved by utilizing learner modeling, domain modeling, and instructional modeling. In the literature of APLS, questions have been raised about the role of individual characteristics that are relevant for adaptation. With several options, a new problem has been raised where the attributes of students in APLS often overlap and are not related between studies. Therefore, this study proposed a list of learner model attributes in dynamic learning to support adaptation and personalization. The study was conducted by exploring concepts from the literature selected based on the best criteria. Then, we described the results of important concepts in student modeling and provided definitions and examples of data values that researchers have used. Besides, we also discussed the implementation of the selected learner model in providing adaptation in dynamic learning.
Prototype mobile contactless transaction system in traditional markets to sup...journalBEEI
1) Researchers developed a prototype contactless transaction system using QR codes and digital payments to support physical distancing during the COVID-19 pandemic in traditional markets.
2) The system allows sellers and buyers in traditional markets to conduct fast, secure transactions via smartphones without direct cash exchange. Buyers scan sellers' QR codes to view product details and make e-wallet payments.
3) Testing showed the system's functions worked properly and users found it easy to use and useful for supporting contactless transactions and digital transformation of traditional markets. However, further development is needed to increase trust in digital payments for users unfamiliar with the technology.
Wireless HART stack using multiprocessor technique with laxity algorithmjournalBEEI
The use of a real-time operating system is required for the demarcation of industrial wireless sensor network (IWSN) stacks (RTOS). In the industrial world, a vast number of sensors are utilised to gather various types of data. The data gathered by the sensors cannot be prioritised ahead of time. Because all of the information is equally essential. As a result, a protocol stack is employed to guarantee that data is acquired and processed fairly. In IWSN, the protocol stack is implemented using RTOS. The data collected from IWSN sensor nodes is processed using non-preemptive scheduling and the protocol stack, and then sent in parallel to the IWSN's central controller. The real-time operating system (RTOS) is a process that occurs between hardware and software. Packets must be sent at a certain time. It's possible that some packets may collide during transmission. We're going to undertake this project to get around this collision. As a prototype, this project is divided into two parts. The first uses RTOS and the LPC2148 as a master node, while the second serves as a standard data collection node to which sensors are attached. Any controller may be used in the second part, depending on the situation. Wireless HART allows two nodes to communicate with each other.
Implementation of double-layer loaded on octagon microstrip yagi antennajournalBEEI
This document describes the implementation of a double-layer structure on an octagon microstrip yagi antenna (OMYA) to improve its performance at 5.8 GHz. The double-layer consists of two double positive (DPS) substrates placed above the OMYA. Simulation and experimental results show that the double-layer configuration increases the gain of the OMYA by 2.5 dB compared to without the double-layer. The measured bandwidth of the OMYA with double-layer is 14.6%, indicating the double-layer can increase both the gain and bandwidth of the OMYA.
The calculation of the field of an antenna located near the human headjournalBEEI
In this work, a numerical calculation was carried out in one of the universal programs for automatic electro-dynamic design. The calculation is aimed at obtaining numerical values for specific absorbed power (SAR). It is the SAR value that can be used to determine the effect of the antenna of a wireless device on biological objects; the dipole parameters will be selected for GSM1800. Investigation of the influence of distance to a cell phone on radiation shows that absorbed in the head of a person the effect of electromagnetic radiation on the brain decreases by three times this is a very important result the SAR value has decreased by almost three times it is acceptable results.
Exact secure outage probability performance of uplinkdownlink multiple access...journalBEEI
In this paper, we study uplink-downlink non-orthogonal multiple access (NOMA) systems by considering the secure performance at the physical layer. In the considered system model, the base station acts a relay to allow two users at the left side communicate with two users at the right side. By considering imperfect channel state information (CSI), the secure performance need be studied since an eavesdropper wants to overhear signals processed at the downlink. To provide secure performance metric, we derive exact expressions of secrecy outage probability (SOP) and and evaluating the impacts of main parameters on SOP metric. The important finding is that we can achieve the higher secrecy performance at high signal to noise ratio (SNR). Moreover, the numerical results demonstrate that the SOP tends to a constant at high SNR. Finally, our results show that the power allocation factors, target rates are main factors affecting to the secrecy performance of considered uplink-downlink NOMA systems.
Design of a dual-band antenna for energy harvesting applicationjournalBEEI
This report presents an investigation on how to improve the current dual-band antenna to enhance the better result of the antenna parameters for energy harvesting application. Besides that, to develop a new design and validate the antenna frequencies that will operate at 2.4 GHz and 5.4 GHz. At 5.4 GHz, more data can be transmitted compare to 2.4 GHz. However, 2.4 GHz has long distance of radiation, so it can be used when far away from the antenna module compare to 5 GHz that has short distance in radiation. The development of this project includes the scope of designing and testing of antenna using computer simulation technology (CST) 2018 software and vector network analyzer (VNA) equipment. In the process of designing, fundamental parameters of antenna are being measured and validated, in purpose to identify the better antenna performance.
Transforming data-centric eXtensible markup language into relational database...journalBEEI
eXtensible markup language (XML) appeared internationally as the format for data representation over the web. Yet, most organizations are still utilising relational databases as their database solutions. As such, it is crucial to provide seamless integration via effective transformation between these database infrastructures. In this paper, we propose XML-REG to bridge these two technologies based on node-based and path-based approaches. The node-based approach is good to annotate each positional node uniquely, while the path-based approach provides summarised path information to join the nodes. On top of that, a new range labelling is also proposed to annotate nodes uniquely by ensuring the structural relationships are maintained between nodes. If a new node is to be added to the document, re-labelling is not required as the new label will be assigned to the node via the new proposed labelling scheme. Experimental evaluations indicated that the performance of XML-REG exceeded XMap, XRecursive, XAncestor and Mini-XML concerning storing time, query retrieval time and scalability. This research produces a core framework for XML to relational databases (RDB) mapping, which could be adopted in various industries.
Key performance requirement of future next wireless networks (6G)journalBEEI
The document provides an overview of the key performance indicators (KPIs) for 6G wireless networks compared to 5G networks. Some of the major KPIs discussed for 6G include: achieving data rates of up to 1 Tbps and individual user data rates up to 100 Gbps; reducing latency below 10 milliseconds; supporting up to 10 million connected devices per square kilometer; improving spectral efficiency by up to 100 times through technologies like terahertz communications and smart surfaces; and achieving an energy efficiency of 1 pico-joule per bit transmitted through techniques like wireless power transmission and energy harvesting. The document outlines how 6G aims to integrate terrestrial, aerial and maritime communications into a single network to provide ubiquitous connectivity with higher
Noise resistance territorial intensity-based optical flow using inverse confi...journalBEEI
This paper presents the use of the inverse confidential technique on bilateral function with the territorial intensity-based optical flow to prove the effectiveness in noise resistance environment. In general, the image’s motion vector is coded by the technique called optical flow where the sequences of the image are used to determine the motion vector. But, the accuracy rate of the motion vector is reduced when the source of image sequences is interfered by noises. This work proved that the inverse confidential technique on bilateral function can increase the percentage of accuracy in the motion vector determination by the territorial intensity-based optical flow under the noisy environment. We performed the testing with several kinds of non-Gaussian noises at several patterns of standard image sequences by analyzing the result of the motion vector in a form of the error vector magnitude (EVM) and compared it with several noise resistance techniques in territorial intensity-based optical flow method.
Modeling climate phenomenon with software grids analysis and display system i...journalBEEI
This study aims to model climate change based on rainfall, air temperature, pressure, humidity and wind with grADS software and create a global warming module. This research uses 3D model, define, design, and develop. The results of the modeling of the five climate elements consist of the annual average temperature in Indonesia in 2009-2015 which is between 29oC to 30.1oC, the horizontal distribution of the annual average pressure in Indonesia in 2009-2018 is between 800 mBar to 1000 mBar, the horizontal distribution the average annual humidity in Indonesia in 2009 and 2011 ranged between 27-57, in 2012-2015, 2017 and 2018 it ranged between 30-60, during the East Monsoon, the wind circulation moved from northern Indonesia to the southern region Indonesia. During the west monsoon, the wind circulation moves from the southern part of Indonesia to the northern part of Indonesia. The global warming module for SMA/MA produced is feasible to use, this is in accordance with the value given by the validate of 69 which is in the appropriate category and the response of teachers and students through a 91% questionnaire.
An approach of re-organizing input dataset to enhance the quality of emotion ...journalBEEI
The purpose of this paper is to propose an approach of re-organizing input data to recognize emotion based on short signal segments and increase the quality of emotional recognition using physiological signals. MIT's long physiological signal set was divided into two new datasets, with shorter and overlapped segments. Three different classification methods (support vector machine, random forest, and multilayer perceptron) were implemented to identify eight emotional states based on statistical features of each segment in these two datasets. By re-organizing the input dataset, the quality of recognition results was enhanced. The random forest shows the best classification result among three implemented classification methods, with an accuracy of 97.72% for eight emotional states, on the overlapped dataset. This approach shows that, by re-organizing the input dataset, the high accuracy of recognition results can be achieved without the use of EEG and ECG signals.
Parking detection system using background subtraction and HSV color segmentationjournalBEEI
Manual system vehicle parking makes finding vacant parking lots difficult, so it has to check directly to the vacant space. If many people do parking, then the time needed for it is very much or requires many people to handle it. This research develops a real-time parking system to detect parking. The system is designed using the HSV color segmentation method in determining the background image. In addition, the detection process uses the background subtraction method. Applying these two methods requires image preprocessing using several methods such as grayscaling, blurring (low-pass filter). In addition, it is followed by a thresholding and filtering process to get the best image in the detection process. In the process, there is a determination of the ROI to determine the focus area of the object identified as empty parking. The parking detection process produces the best average accuracy of 95.76%. The minimum threshold value of 255 pixels is 0.4. This value is the best value from 33 test data in several criteria, such as the time of capture, composition and color of the vehicle, the shape of the shadow of the object’s environment, and the intensity of light. This parking detection system can be implemented in real-time to determine the position of an empty place.
Quality of service performances of video and voice transmission in universal ...journalBEEI
The universal mobile telecommunications system (UMTS) has distinct benefits in that it supports a wide range of quality of service (QoS) criteria that users require in order to fulfill their requirements. The transmission of video and audio in real-time applications places a high demand on the cellular network, therefore QoS is a major problem in these applications. The ability to provide QoS in the UMTS backbone network necessitates an active QoS mechanism in order to maintain the necessary level of convenience on UMTS networks. For UMTS networks, investigation models for end-to-end QoS, total transmitted and received data, packet loss, and throughput providing techniques are run and assessed and the simulation results are examined. According to the results, appropriate QoS adaption allows for specific voice and video transmission. Finally, by analyzing existing QoS parameters, the QoS performance of 4G/UMTS networks may be improved.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology
1. Bulletin of Electrical Engineering and Informatics
Vol. 9, No. 1, February 2020,pp. 396~402
ISSN: 2302-9285,DOI: 10.11591/eei.v9i1.1852 396
Journal homepage: http://beei.org
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier
for wireless sensor networks using 0.13-m technology
S. A. Z. Murad1, A. Azizan2, A. F. Hasan3
1,2
School of Microelectronic Engineering, Kampus Pauh Putra, Universiti Malaysia Perlis, 02600 Arau, Perlis, Malaysia
3
Faculty of Engineering Technology, Aras 1, Blok S, Kampus UniCITI Alam, Sungai Chuchuh, Padang Besar
02100 Perlis, Malaysia
Article Info ABSTRACT
Article history:
Received Aug 30, 2019
Revised Oct 24, 2019
Accepted Dec 28, 2019
This paper describes the design topology of a ultra-low power low noise
amplifier (LNA) for wireless sensor network (WSN) application.
The proposed design of ultra-low power 2.4 GHz CMOS LNA
is implemented using 0.13-µm Silterra technology. The LNA benefits of low
power from forward body bias technique for first and second stages.
Two stages are implemented in order to enhance the gain while obtaining
low power consumption for overall circuit. The simulation results show that
the total power consumed is only 0.45 mW at low supply voltage of 0.55 V.
The power consumption is decreased about 36% as compared with
the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input
third order intercept point (IIP3) of -2 dBm are achieved. The input return
loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB,
respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1
.
Keywords:
Forward body bias
Gain
Low noise amplifier
Low power
Noise figure
This is an open access article under the CC BY-SA license.
Corresponding Author:
S. A. Z. Murad,
School of Microelectronic Engineering,
KampusPauh Putra, Universiti Malaysia Perlis,
02600 Arau, Perlis, Malaysia.
Email: sohiful@unimap.edu.my
1. INTRODUCTION
A wireless sensor network (WSN) develops very fast in the market because it offers great functions.
The WSN has basic specifications such as the accuracy, flexibility, reliability, expenses, power consumptions
and the difficulty of designing [1]. Part of that, the power consumption is the most important specification
due to the battery powered of the nodes [2]. Consequently, this specification leads to a great development
of CMOS RF usage in a research area. The reasons are due to the low cost and size which are capable
to be fabricated on a single chip and can be integrated in many applications [3].
In the front-end of the RF receiver chain, LNA is a block that cannot be replaced [4-6].
The functionsof LNA are to boost the signal received from the receiving antenna and transmit the signal with
high gain to minimize noise contribution of the next stages [7, 8]. There are many publications of CMOS
LNAs focusing on gain [9-11]. However, only a few recent published works are related to the very low
power LNA. In [12], the topology of a two-stage cross-coupling cascaded common gate (CG) is adapted
by using 0.18 µm TSMC process. It achieves gain of 16.8 dB and power consumption of 2.16 mW.
But the inductor is fabricated separately with a large value which is 32 nH. Besides, by using a current-reused
topology can also obtain low power consumption [13]. It achieves gain of 14 dB and 2.45 mW. The proposed
design uses a few inductors and consequently increases the chip size.
2. Bulletin of Electr Eng & Inf ISSN: 2302-9285
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for… (S. A. Z. Murad)
397
Hence, the aim of this work is to design a LNA with low power consumption and other specification
within the expectation range. The power dissipation of the LNA must be minimized in order to extend
the battery lifetime of the wireless sensor nodes [14]. Therefore, a design based on forward body bias with
two stages is presented [15]. In order to reduce power consumption, forward body bias is an effective
technique. This is because it will lower down the supply voltage by decreasing the threshold voltage and thus
the power consumption can be reduced [15-17]. The dc bias at the bulk terminal of transistor can
be varied to control the threshold voltage [18]. The similar work has been presented in [7]. However,
the second stage is not connected correctly as a cascade topology. Therefore, the simulation results are
questionable. The proposed work also performed pre-layout simulation results without the layout. This paper
is organized as follows: in Section 2, the forward body bias technique is explained, the proposed LNA circuit
design is analyzed in Section 3. Section 4 presents the simulation results achieved from the proposed circuit
design and finally, Section 5 concludesoverall achievement.
2. FORWARD BODY BIAS TECHNIQUE
Due to the simplicity of the forward body bias technique; it is used in this topology as to lower
down the value of power consumption of the LNA [15] which will be discussed in details as below.
This topology of LNA is implemented and designed by using a 0.18-μm CMOS technology [15]. The LNA
operates at 2.4 GHz with only 0.6 V of supply voltage and achieves 2.88 dB of NF, 10.1 dB of gain,
and power consumption is 0.84 mW. Figure 1 shows the schematic of the forward body bias topology.
Typically, the equation between the threshold voltage and the body-source voltage is given as [16].
V = V +γ( 2 -V - 2 )
th th0 bs
f f
(1)
where Vtho is the threshold voltage for Vbs = 0, γ is a process-dependent parameter,
f is a semiconductor parameter with a typical value in the range of 0.3-0.4 V, Vbs is the source-to-body
voltage. From Figure 2, it can be seen that the Vth is decreased when Vbs is increased. Therefore, the low
voltage and low power LNA can be achieved in the design without affecting other device characteristics
of gain, linearity and noise figure [15]. The forward body bias technique has low linearity inherently but can
be done with simplicity which resulted to a smaller size of the LNA.
Figure 1. The schematic design of two stages LNA Figure 2. The calculated threshold voltage of NMOS
when varying VBS from 0 to 0.5V [19]
3. LNA CIRCUIT DESIGN
The design approached is based on previous published technique which is forward body bias [14]
and single forward body bias technique [19-20]. The proposed LNA is shown in Figure 3. The technique
is employed forward body bias technique for both stages. This LNA operates at low supply voltage which
is 0.55 V. The cascode structure is employed in the first stage and the second stage which consist of transistor
M1, M2 and M3, M4, respectively. The suitable sizes for transistors are chosen as to ensure an acceptable
gain at low bias voltage. The size of M1 and M2 is set to 130 µm/0.13 µm with 13 fingers and 10 µm widths
while the size of M3 and M4 is set to 120 µm/0.13 µm with 12 fingers and 10 µm widths. The bulk voltage
(VB) of M1, M2, M3 and M4 is 0.3 V through R4 is chosen in order to ensure that the transistors operate
3. ISSN: 2302-9285
Bulletin of Electr Eng & Inf, Vol. 9, No. 1, February 2020 : 396 – 402
398
in a saturation region. The inductor L1 affects input matching and also input stage gain.
Moreover, the inductor L1 and capacitor C1 provides DC path for transistor M1. Capacitor C2 is resonates
with L2 as to improve a gain and an input matching while to guarantee that the design operate at frequency
2.4 GHz. A C5 provides DC path to the next stage of the LNA design.
Figure 3. The schematic design of two stages LNA
4. SIMULATION RESULTS
In order to generate S-parameters,noise figure, stability and linearity, the simulations are carried out
using the Cadence Spectre analog design environment (ADE). Hence, the simulated results that are obtained
from two stages forward body bias technique at 2.4 GHz are presented in this section. The overall circuit
operates at 0.55 V supply voltage and draws 820 µA of the total current. The pre-layout and post-layout
results of S11 are illustrated in Figure 4. The input return loss, S11 for pre-layout is -23.2 dB while for
post-layout is -17.6 dB at 2.4 GHz. From the Figure 2, it can be seen that both pre-layout and post-layout
results are agreed to each other. The differences is due to the extracted parasitic that exists during
the simulation hasaffected the input matchingof the LNA [14]. But, the value is still in the acceptable range.
Figure 5 depicts the output return loss (S22) of the proposed two stages LNA. It can be seen that both
the pre-layout and the post-layout are -16.6 dB and -12.29 dB respectively. As can be seen in Figure 5,
the post-layout curve is shifts to the right from the operating frequency, 2.4 GHz. This happens due
to the parasitic of routing, capacitance,inductance and output pad.
Figure 4. The input return loss (S11) of two
stages LNA
Figure 5. The output return loss (S22) of two
stages LNA
Figure 6 depicts the voltage gain (S21) of the proposed two stages forward body bias with cascode
configurations LNA. From the pre-layout simulation results, the peak voltage gain, S21 of 19.71 dB
4. Bulletin of Electr Eng & Inf ISSN: 2302-9285
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for… (S. A. Z. Murad)
399
is observed for overall circuit. But, the gain is degrading to 15.05 dB during post-layout simulation.
The reason is because of the existence of the extracted parasitic in load inductors. Figure 7 illustrates
the pre-layout and post-layout simulations results for the noise figure (NF). The NF of 4.9 dB and 5.9 dB
is achieved for the pre-layout and post-layout at 2.4 GHz, respectively. The increasing of NF is due to
the parasitic effects.Moreover, the transmission lines from the input pad to the inductor and gate of transistor
can be modelled by a resistor which can also contribute to the noise. In addition, there are more components
for the proposed two stages LNA which can also contribute to the noise for overall performance.
However, the NF achieved from this LNA circuit is within the specifications performance.
Figure 6. The voltage gain (S21) of two stages LNA Figure 7. Noise Figure of the proposed LNA
Linearity is performed as it can determine the performances of the LNA. It occurs when
an unwanted signal presents nearer to the operating frequency. The higher linearity is more desirable.
First, the linearity of the proposed LNA is simulated by the input 1 dB compression point (IP1dB).
As illustrates in Figure 8, the simulated IP1dB of -15 dBm is obtained at 2.4 GHz. Meanwhile, the third-order
intercept point (IIP3) is the interception of the first-order output curve and the third-order intermodulation
output curve at 2.4 GHz is shown in Figure 9. As can be seen in Figure 9, the IIP3 for the proposed two
stages LNA of -2 dBm is achieved. The stability factor from the proposed LNA which is more than one
is achieved asshown in Figure 10. Therefore, the proposed LNA is unconditionalstable.
Figure 8. Noise Figure of the proposed LNA Figure 9. Simulated result of IIP3 of two stages LNA
The layout of the proposed two stages LNA is illustrated in Figure 11. All components are designed
on-chip. In the layout, spiral inductors and metal-insulator-metal (MIM) capacitors are used due to high
quality factorand low losses, respectively. The total layout area is 0.99 mm × 0.98 mm which consists of two
GSG pads, three dc pads, four inductors, DC block, five capacitors, four RF resistors and four transistors.
The layout will be tape out in the future.
5. ISSN: 2302-9285
Bulletin of Electr Eng & Inf, Vol. 9, No. 1, February 2020 : 396 – 402
400
Figure 10. Stability of the proposed two stages LNA Figure 11. The layout of the proposed two
stages LNA
The overall post-layout results performances comparison between the proposed LNA with recently
published works is summarized in Table 1. This proposed LNA consumes only 0.45 mW for overall circuit
with 0.55 V supply voltage. The LNA cannot be replace or remove in the RF receiver front-end [21].
Therefore, it should deliver a significant gain to minimize the noise contribution of the subsequent stages and
to amplify the attenuated signal received by the antenna so that it can be efficiently handled by the next
stages such as mixer and VGA [4]. A low voltage and low power LNA’s performance is evaluated based
on figures of merits (FOMs). There are different FOMs are commonly used in the previous works [22].
One of the FOM of the LNA can be calculated based on the ration of power gain to the power dissipation
and NF performance asrepresented in (2).
( )
1
( )
[mW ] =
( 1)
−
−
abs
abs DC
Gain
FOM
NF P
(2)
where, abs is the absolute value of gain and NF [23]. Comparing with the other works, the proposed LNA
obtains the lowest power consumption. Besides, the linearity performance of this work is better than others.
Meanwhile, gain is comparable by considering a low supply voltage. Referring to [21], high gain and good
FOM are achieved without linearity (IIP3) performance. References [24] also obtained high gain with high
power consumption. Based on the calculated FOMs in Table 1, the proposed LNA shows the best
performancesthan otherproposed LNAs.
Table 1. Overall performances comparison of the proposed LNA (post-lyout)
Parameter [13] [21] [24] [25] This work
CMOS Technology (m) 0.13-µm 0.18-µm 0.18-µm 0.18-µm 0.13-µm
Supply Voltage (V) 0.8 1.2 1.8 1.0 0.55
Frequency(GHz) 3.7 2.4 2.4 2.4 2.4
Gain (dB) 14 20 20.10 18.2 15.1
S11, S22 (dB) -10.6, N/A <-13.5, N/A N/A N/A -17.6,-12.3
NF (dB)
IP1dB (dBm)
IIP3 (dBm)
Power (mW)
FOM (mW−1
)
Chip Size (mm2
)
2.0
N/A
10.5
2.45
1.82
N/A
5.6
N/A
N/A
0.70
8.41
0.02
3.2
N/A
-2.4
1.30
6.04
0.03
3.4
-15
-4.32
0.97
6.37
0.04
5.9
-15
-2.0
0.45
7.19
0.97
5. CONCLUSION
A very low power 2.4 GHz two stages CMOS LNA using forward body bias technique has been
proposed in this work. As the forward body bias technique allows for the reduction of the threshold voltage
and thus reduces the power consumption, therefore the technique was implemented in this work. Two stages
LNA is proposed as to enhance the overall gain. In order to get low power consumption, this circuit
6. Bulletin of Electr Eng & Inf ISSN: 2302-9285
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for… (S. A. Z. Murad)
401
is designed which capable to operate at a low supply voltage which is 0.55 V. The post-layout results show
that the power consumption of 0.45 mW is obtained with the FOM of 7.19 mW-1. The power consumption
is decreased about 36% as compared with the previous work. The overall chip size is 0.97 mm 2.
The simulation results validate peak performance at 2.4 GHz that suitable for wireless sensor
network applications.
ACKNOWLEDGEMENTS
The author would like to acknowledge the support from the Fundamental Research Grant Scheme
(FRGS) under a grant number of FRGS/2/2013/TK02/UNIMAP/02/4 from the Ministry
of Education Malaysia.
REFERENCES
[1] S. A. Z. Murad, S. N. Mohyar, A. Harun, M. N. M. Yasin, I. S. Ishak and R. Sapawi, "Low noise figure 2.4 GHz
down conversion CMOS mixer for wireless sensor network application," 2016 IEEE Student Conference
on Research and Development (SCOReD), Kuala Lumpur, pp. 1-4, 2016.
[2] S. Lee, I. Choi, H. Kim and B. Kim, "A sub-mW fully integrated wide-band receiver for wireless sensor network,"
in IEEE Microwave and Wireless Components Letters, vol. 25, no. 5, pp. 319-321, May 2015.
[3] H. Aljarajreh, M. B. I. Reaz, M. S. Amin, H. Husain, “An active inductor based low noise amplifier for RF
receive,” Elektronika Ir Elektrotechnika, vol. 19, no. 5, pp. 49-52, Febuary 2013.
[4] S. A. Z. Murad, R. C. Ismail, M. N. M. Isa, M. F. Ahamd, W. B. Han, "High gain 2.4 GHz CMOS low noise
amplifier for wireless sensor network applications," 2013 IEEE International RF and Microwave Conference
(RFM), Penang, pp. 39-41, 2013.
[5] T. Z. A. Zulkifli, A. Marzuki and S. A. Z. Murad, "UWB CMOS low noise amplifier for mode 1," 2017 IEEE Asia
Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Kuala Lumpur,
pp. 117-120. 2017.
[6] Murad, Sohiful Anuar Zainol, A. F. Hasan, A. Azizan, A. Harun, J. Karim, "A concurrent dual-band CMOS low
noise amplifier at 2.4/5.2 GHz for WLAN applications," in Indonesian Journal of Electrical Engineering
and Computer Science (IJEECS), vol. 14, no. 2, pp. 555-563, May 2019.
[7] A. Azizan, S. A. Z. Murad, M. M. Ramli and R. C. Ismail, "Design of a 2.4 GHz CMOS LNA using two-stage
forward body bias technique for WSN application," 2015 IEEE Student Conference on Research and Development
(SCOReD), Kuala Lumpur, 2015, pp. 415-417.
[8] W. Jhen-Ji, et. al., “A multi-band low noise amplifier with wide-band interference rejection improvement,”
International Journal of Electroninc and Commununication (AEU), vol. 70, no. 3, pp. 320-325, March 2016.
[9] Singh, Rashmi and Rajesh Mehra, “Low Noise Amplifier using Darlington Pair At 90nm Technology,”
in International Journal of Electrical and Computer Engineering (IJECE), vol. 8, no. 4, pp. 2054-2062,
August 2018.
[10] Muhamad, Maizan, et. al., "Linearity improvement of differential CMOS low noise amplifier," Indonesian Journal
of Electrical Engineering and Computer Science (IJEECS), vol. 14 no. 1, pp. 407-412, April 2019.
[11] Abbas, Mohammed Nadhim, and Farooq Abdulghafoor Khaleel, “Mixed Linearity Improvement Techniques
for Ultra-wideband Low Noise Amplifier,” in International Journal of Electrical and Computer Engineering
(IJECE), vol. 8, no. 4, pp. 2038-2045, August 2018.
[12] M. Zhang, and Z. Li, “Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network
applications,” Journal of Semiconductor, vol. 33, no. 10, 2012.
[13] R. Habib, and H. Ahmad, “A high linearity CMOS low noise amplifier for 3.66 GHz applications using
current-reused topology,” Microelectronic Journal, vol. 44, no. 4, pp. 301-306, April 2013.
[14] T. Sasilathaa, and J. Rajab, “A 1 V, 2.4 GHz low power CMOS common source LNA for WSN applications,”
International Journal of Electronic and Communication (AEU), vol. 64, no. 10, pp. 940-946, October 2010.
[15] J. Wu, Y. Lin and Y. Tsai, “A sub-mW CMOS LNA for WSN applications,” 2012 Asia Pacific Microwave
Conference Proceedings, Kaohsiung, pp. 899-901, 2012.
[16] A. Dehqan, E. Kargaran, K. Mafinezhad and H. Nabovati, "An ultra low voltage ultra low power CMOS UWB
LNA using forward body biasing," 2012 IEEE 55th International Midwest Symposium on Circuits and Systems
(MWSCAS), Boise, ID, pp. 266-269, 2012.
[17] A. Azizan, S. A. Z. Murad, R. C. Ismail and M. N. M. Yasin, “A Review of LNA topologies for wireless
applications,” 2014 2nd International Conference on Electronic Design (ICED), Penang, pp. 320-324, 2014.
[18] W. Quizhen, et. al., “Design and analysis of a 3.1-10. GHz UWB low noise amplifier with forward body bias
technique,” International Journal of Electronic and Commununication (AEU), vol. 69, no. 1, pp. 119-125,
January 2015.
[19] T. Taris, J. Begueret and Y. Deval, "A 60µW LNA for 2.4 GHz wireless sensors network applications," 2011 IEEE
Radio Frequency Integrated Circuits Symposium, Baltimore, MD, pp. 1-4. 2011.
[20] A. Azizan, and S. A. Z. Murad, “A 0.3 mW 2.4 GHz low power low noise amplifier using forward body bias
technique for wireless sensor,” in Jurnal Teknologi, vol. 78, no. 1, pp. 31-37, January 2016.
7. ISSN: 2302-9285
Bulletin of Electr Eng & Inf, Vol. 9, No. 1, February 2020 : 396 – 402
402
[21] S. V. M. Bonehi, A. Ruder, S. Aghaie, I. Subbiah, R. Wunderlich and S. Heinen, "Design of ultra low power
cascaded inductorless LNA for Wireless Sensor Network application," 2016 12th Conference on Ph.D. Research
in Microelectronics and Electronics (PRIME), Lisbon, pp. 1-4. 2016.
[22] Z. Li, Z. Wang, M. Zhang, L. Chen, C. Wu and Z. Wang, "A 2.4 GHz Ultra-Low-Power Current-Reuse CG-LNA
With Active Gm -Boosting Technique," in IEEE Microwave and Wireless Components Letters, vol. 24, no. 5,
pp. 348-350, May 2014.
[23] C. Chang, J. Chen and Y. Wang, "A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias
Technology," in IEEE Microwave and Wireless Components Letters, vol. 19, no. 3, pp. 176-178, March 2009.
[24] J. Roya, et. al., “A low power low noise amplifier employing negative feedback and current reuse techniques,”
Microelectronic Journal, vol. 49, pp. 49-56, March 2016.
[25] K. Atiyeh, et. al., “An inductor-less Sub-mW low noise amplifier for wireless sensor network Applications,”
in Integration, vol. 52, pp. 316-322, January 2016.
BIOGRAPHIES OF AUTHORS
Sohiful Anuar Zainol Murad received the B.Eng degree in Electronic Engineering from Saga
University, Japan, in 2000, the Master of Science in Electronic Systems Design Engineering
from the Malaysia Science University, Malaysia in 2004 and PhD in electronics from Kyushu
University, Japan in 2011. Currently he is a senior lecturer in the School of Microelectronic
Engineering, Universiti Malaysia Perlis, Malaysia. His research interests include electronic
circuits design, analog and radio frequency integrated circuit design. He has over 90 publications
including journals and proceedings published in SCOPUS and five academic books.
Anishaziela Azizan received the B. Eng degree in Electrical Engineering (Electronics) from
Universiti Teknologi Malaysia, in 2011. She obtained her Master of Science in Microelectronic
Engineering at Universiti Malaysia Perlis. Currently she is a lecturer in Faculty of Engineering
Technology in Electronic Department, Universiti Malaysia Perlis. Her research interest includes
analog and radio frequency integrated circuit design. She has published many conference
proceedings and also journal papers.
Ahmad Fariz Hasan received the B Eng. degree in Electrical Engineering (Telecommunication)
from Universiti Teknologi Malaysia, in 2007. He obtained his M.Eng in 2012 in Electrical
Engineering at Universiti Teknologi Malaysia. He is currently pursuing his Phd. in Electronic
Engineering at the School of Microelectronic Engineering, Universiti Malaysia Perlis.
His research interest includes the areas of design front-end RF circuit. He has published many
conference proceedings as well as journal papers in local and international journals.