Zhu Yu is a female electronic engineer born in 1987 with a M.S. degree from Harbin Institute of Technology. She has over 3 years of work experience as an FPGA engineer developing digital filters, embedded software, and Linux drivers. Some of her project experiences include designing data acquisition systems, frequency calibration algorithms, serial communication cards, and satellite payload simulators. She is proficient in Verilog, C/C++, and embedded Linux development.

1.  Basic Information
Name Zhu Yu Address Hai Dian, Beijing
Gender Female Date of Birth 1987.11.11
Education Academic M.Sdegree Field Electronic Engineering
Email 461457613@qq.com Mobile Number 13641363647
 Education
2011.9-2013.7 Master of Automatic Test and Control Harbin Institute of Technology (985,211)
2007.9-2011.7 Bachelorof AutomaticTest and Control Harbin Institute of Technology (985,211)
 Work Experience (3 years)
FPGAengineer and Embedded Software Engineer of Beijing Pansino-Solutions.
Be responsible for Digital unit FPGAdesign, including DDC,FIR and CIC filter.
Be responsible for FPGAdesign, development , debug and verification.
Be responsible for related documentation of requirement, architecture, design specification and verification.
Be responsible for Embedded systemmigration.
Be responsible for developing and debugging Linux softwarein Xilinx SDK.
 Project Experience
1. Embedded Software design 2015.7-present
The platform of ZYNQ is adopted, assisted with A/D converter, Ethernet interface and DDR3. It has 8 channels
and is used for DAQ in Wind tunnel experiments. My responsibilities are as follows:
 Responsible for transplanting embedded operating system Petalinux on the DAQ card based on ZYNQ
platformxc7x010.
 Responsible for building the Petalinux project, modifying the kernel, the rootfs, device tree and U-BOOT.
Responsible for booting Petalinux from SD and QSPI flash. SD card can be 4GB or 64GB. I divide the 64GB
into 2 partitions: one for booting, which uses fat32 filesystem. The other for storing massage data, which
uses ext3 filesystem.
 Responsible for developing the software in C language for identifying the lan board , acquiring the getting
the mass data from the Ethernet and sending to the memory of PC.
Technology Value:
The distributed data acquisition systemcan be easily used in the Wind tunnel experiments.
2. Design and implement DDC on Xilinx Virtex-5 2015.5-2015.6
The data acquired by A/D converter is multiplied by a DDS signal with its center frequency can be tuned . Then
it goes through a CIC and is processed by a half-band fir filter.
 Responsible for the FPGA RTL coding, testing(including simulation and on board), debugging of the
Digital interface, PXIe and DDR2 controller modules.
Technology Value:
Through digital signal processing technology, we reduce thefrequency of an IF signal.
3. Design and implement Dual-mode tame rubidium clock card 2014.10-2015.4
The card can receive both GPS and BeiDou Satellite messages. It provides the IRIG-B time signal with its edge is
aligned with theGPS 1PPS signal. It has complicated frequency calibration algorithm.
Responsibility:
 Develop an algorithm of frequency calibration and implement it in Spartan6 FPGA.
 Implement PCI interface using theinternal PCI IP.
 RTL coding for controlling the GPS chip, the RTC chip, the DAC chip and the ru clock chip .
 Develop theIIC interface , the serial interface and DAC interface.

2. Technology Value:
We can create fairly accurate time source.
4. Design and implement Intelligent serial card 2013.11-2014.9
It has 8 channels .Each channel can be configured as RS232、RS422 or RS485 mode independently. Each channel
also has 2MB SDRAM buffer. RS232 rates rate from 1bps to 1Mbps. RS422 and RS485 rate from 1bps to
10Mbps. In theAlteraEP3C40 FPGARTL design,
 Develops a queuing strategy by querying the capacity of each partition and develop the SPI flash m25p128
interface .
 RTL coding for SDRAM controller , theuart module, the controller of si5338 and PLX9054 interface.
Technology Value:
It can be widely used in serial communication because of its strong compatibility.
5. Thedevelopment of the satellite payload data simulator using Xilinx Virtex-5 2012.7-2013.6
Payload of remote sensing satellites is expensive, easily damaged. Developed a payload simulator bases on
PXIe×4 interface and SLC NAND Flash array. It can output 24-channel LVDS data and timing which is compliant
with satellites in orbit. My responsibilities are as follows:
 Responsible for schematic design, chip selection(especially power chips), pin assignment, module,
simulation, RTL designing, coding, debugging of PCIe DMA, the eeprom controller , the NAND Flash
controller and the LVDS framing and doing timing constraints.
 Responsible for CVI software development for PC download the image data to the NAND Flash
through the PCIe interface.
 Responsible for co-debugging with other teams.
Technology Value:
It can replace thevery expensive payload on thesatellite.
6.The development of PCI WDM windows driver of Windows XP 2011.2-2012.5
 Develop PCI driver based on WDM. It supports Configuration read and write, PIO and DMA read
and write using Driver Studio software. The driver has Power Management and PNP function.
Technology Value:
It can make PC identify and control the PXI DAQ card based PCI.
 Technical Ability
Development Tools
Xilinx: ISE,Vivado,SDK
Mentor:Modelsim
Altera: Quartus
MathWorks:Matlab
Jungo: Windriver
Windows Driver WDM/WDF Development
Embedded Linux Petalinux Development
SVN
Programmable Language
Verilog
C, C++
Python
 Award
Twice Special scholarship

3. Once National scholarship
First prizein Virtual instrument design competition
 English Level
CET-6 (571)
Fluent in reading and writing, moderate in speaking
 My Blog
http://blog.csdn.net/christne1225i
 Hobbies
Playing badminton, singing, cooking