The document provides a summary of Sourav Samanta's qualifications and experience. It summarizes that he is a computer engineering graduate from Arizona State University seeking a full-time position in digital/mixed-signal design. He has competencies in RTL design, verification, physical design, and implementation of VLSI CAD algorithms in Python. His experience includes intern work at Synopsys and graduate assistant work at ASU.

1. SOURAV SAMANTA
3539 Haig Street, Santa Clara, CA - 95054
• Mobile: +1-480-275-1094 • Email ID: ssamant4@asu.edu • https://www.linkedin.com/pub/sourav-samanta/a1/985/26a
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SUMMARY
Computer Engineering Graduate from Arizona State University with specialization in VLSI Design, seeking Full-time opportunities in Digital /
Mixed-signal, ASIC / FPGA / SoC Design, Verification and Automation from September 2016 with competencies in:
 Hardware Modelling using Verilog (RTL Design) and Functional Verification using SystemVerilog
 RTL to GDSII Flow: EDA Synthesis, APR, CTS, Static Timing and Power Analysis (UPF standards)
 Standard Cell Library Design and Characterization
 Full Custom Physical Design and Layout Verification including Custom Memory Design: Register File
 Implementation of VLSI CAD Algorithms in Python for High Level & Logic Synthesis and Optimization
EDUCATION
 Ira A. Fulton Schools of Engineering, Arizona State University, Tempe, AZ May 2016
Master of Science in Computer Engineering (Electrical Engineering) GPA: 3.46/4
 KIIT University, Bhubaneswar, India May 2010
Bachelor of Technology in Electronics and Telecommunication Engineering GPA: 9.07/10
WORK EXPERIENCE
 Technical Intern (Design group - Analog and Mixed-Signal) at Synopsys Inc. June 2016 – Present
Responsibilities included Test Plan preparation and Test Execution for Mixed-signal Simulation Flow on Synopsys VCS, VCS-MX tools and
Creating Technical documents.
 Graduate Service Assistant – Grader (Digital Design Fundamentals, Circuits I) at Arizona State University Aug 2015 – May 2016
 Systems Engineer at Tata Consultancy Services (TCS) Aug 2010 – July 2014
Worked as a SAP IS-U Billing Software Functional Consultant for Australian client AGL Energy and responsibilities included Requirements
Gathering, Feasibility Analysis, Blueprinting, Application Support, Software Design-Development and Testing.
TECHNICAL SKILLS
 ElectronicDesign Automation Tools: Cadence Virtuoso (in Synopsys 32nmPDK), Cadence (ELC, Abstract Generator, RC, SoC Encounter),
Synopsys (Hercules – DRC LVS, StarRC, PrimeTime), Xilinx Vivado Design Suite
 Simulation: Synopsys (VCS, VCS-MX, CustomSim, HSPICE), ALDEC (Active-HDL, Riviera PRO), MG - ModelSim, Cadence Spectre
 Programming Languages: C, C++, Python, Matlab, Java (Oracle Certified)
 Hardware Description Languages, Verification & Scripting: Verilog, System Verilog, Perl scripting, TCL (beginner), Unix commands
 Coursework: Digital Systems and Circuits, Computer Systems I, Computer Systems II, Hardware Design and Verification Languages, VLSI
Design, Analog Integrated Circuits, Computer Architecture I, Operating Systems, Algorithms for Synthesis and Optimization of Digital
Systems, Object Oriented Programming using C++ (Under graduate)
PROJECTS
 Design of Standard Cell Library & Characterization Fall 2014
 Designed standard cells (INVX02, NOR2X05, NAND3X03) using Synopsys 32nm PDK in Cadence Virtuoso.
 Hercules DRC and LVS used for physicalverification & Synopsys StarRC used for parasitic extraction.
 Performed Characterization of the cells using Cadence ELC and generated .lef files using Abstract Generator.
 Circuit simulations carried out using Synopsys HSPICE.
 RTL-to-GDSII flow of a 5 port Network-on-ChipRouterin 32nm PDK Spring 2015
 Designed a NoC Router in Verilog with X-Y Routing logic and buffered input ports (synchronous FIFO).
 EDA synthesis automation carried out using TCL scripts.
 Optimized area and EDP and performed timing closure through pre-CTS/ post-CTS/ post-route timing optimization and ECO flows in
Encounter, power and timing analysis in Primetime.
 Design andVerification of I2C Masterand Slave Controllerusing Verilog Spring 2015
 Designed an I2C Master and Slave Controller along with Serial-Parallel/ Parallel-Serial converter modules in Verilog.
 Developed a test bench for Verification using Bus Functional Modelfor Core read and write functionality.
 Verification of AND gate and D-FF using SystemVerilog Spring 2015
 Built an Objected Oriented Verification Environment using SystemVerilog classes which included Driver, Receiver, ScoreBoard & DUT.
 Used Virtual Interfaces & Clocking blocks to build theverification environment. Verified AND gate & D-FF using OOPs principles.
 Design of a 16 X 16 RegisterFile with one read and one write port Spring 2015
 Designed a 16 entry, 16 bit wide Register File with 1 read and 1 write port using 32nm PDK in Cadence Virtuoso.
 Physical Design optimizations included diffusion sharing to reduce layout area and load capacitance.
 Design of a simple Microprocessor using Verilog on Basys3 FPGA board Fall 2015
 Designed a simple 4 cycle (fetch, decode, execute, store) Microprocessor using Verilog.
 Used Xilinx Vivado Design Suite to implement the design on a Basys3 FPGA board (Artix-7).
 VLSI CAD: Scheduling Algorithms of Data Flow Graphs for High Level Synthesisusing Python Fall 2015
 Implemented Scheduling Algorithms (MLRC and MRLC) of DataFlow Graphs for HLS in Python using List based scheduling heuristics
and the exact solution using Integer Linear Programming.