Space Codesign's overview of SpaceStudio system-level hardware/software co-design technology for ARM Technology Symposium Japan 2014 (Tokyo Shinagawa, October 2014)
Space Codesign's presentation to TandemLaunch with intro to electronics design technology (CAD), EDA industry history and career insights startup versus corporate!
Cleaning Code - Tools and Techniques for Large Legacy ProjectsMike Long
This document discusses techniques for cleaning and restoring large legacy software projects. It begins by defining what constitutes a large legacy project and restoration project. It then discusses how codebases can become messy over time due to factors like explosive growth and lack of quality processes. The document outlines some of the tools and techniques that can be used for identifying and removing waste from large legacy code, including tools for visualizing code quality, detecting duplicate code, and identifying unused code. It stresses that legacy restoration requires managing culture change. The document concludes that prevention is better than cure, legacy software is still valuable, and there is always a business case for restoration if it can be properly quantified and proven.
A design methodology and a language framework which contributes to providing a solid, scalable framework for developing next-generation silicon-based systems.
The document proposes a model for dynamically organizing edge computing nodes into micro clouds to provide edge computing as a service. The model involves grouping nodes into clusters, clusters into regions, and regions into a topology. Micro clouds are ephemeral cloud-like structures serving local requests before reaching the traditional cloud. Protocols for health checking, cluster formation, and listing the system state are proposed. The model is inspired by cloud architecture and aims to lower latency by processing data closer to its source.
ASIT provides best training on "Object Oriented Programming" Course , invites lot of people with technical back ground and experienced HR from corporate world as a part of pre-placement training, this actually helps us to perform better in our interviews. For more details please visit our website.
This document summarizes the evolution of the RISC-V software ecosystem from 2015 to 2020. It describes how initial ports of key software in 2015, like GCC and Linux, have expanded to include upstream support in most open source software projects today. It outlines remaining priorities like completing support for specifications and filling gaps in programming language and application software support. The document concludes by encouraging continued collaboration to further mature the RISC-V software ecosystem.
Space Codesign at TandemLaunch Lunch & Learn 20150414Gary Dare
Space Codesign 's presentation by Gary Dare to Montreal TandemLaunch hardware-oriented startup incubator (accelerator) on April 14, 2015. This is a more general presentation on electronics design technology and history of the EDA industry which originated as startups around 1980. Not a product pitch but highlights of SpaceStudio innovation is included. The intended audience is general rather than just electronics and software engineers, and technical management.
This document describes Space Codesign's ESL hardware/software co-design flow for ARM processor-based FPGAs. It allows designers to explore architecture and perform hardware/software partitioning, simulation and monitoring at a high level in SystemC before generating RTL and prototypes. Key benefits include extensive automation, transparent performance analysis, and no recoding needed between SystemC and VHDL. An example Motion JPEG demo shows the ARM Cortex-A9 core achieving over 700 fps compared to under 100 fps for a MicroBlaze and 250+ fps for a Leon3.
Space Codesign's presentation to TandemLaunch with intro to electronics design technology (CAD), EDA industry history and career insights startup versus corporate!
Cleaning Code - Tools and Techniques for Large Legacy ProjectsMike Long
This document discusses techniques for cleaning and restoring large legacy software projects. It begins by defining what constitutes a large legacy project and restoration project. It then discusses how codebases can become messy over time due to factors like explosive growth and lack of quality processes. The document outlines some of the tools and techniques that can be used for identifying and removing waste from large legacy code, including tools for visualizing code quality, detecting duplicate code, and identifying unused code. It stresses that legacy restoration requires managing culture change. The document concludes that prevention is better than cure, legacy software is still valuable, and there is always a business case for restoration if it can be properly quantified and proven.
A design methodology and a language framework which contributes to providing a solid, scalable framework for developing next-generation silicon-based systems.
The document proposes a model for dynamically organizing edge computing nodes into micro clouds to provide edge computing as a service. The model involves grouping nodes into clusters, clusters into regions, and regions into a topology. Micro clouds are ephemeral cloud-like structures serving local requests before reaching the traditional cloud. Protocols for health checking, cluster formation, and listing the system state are proposed. The model is inspired by cloud architecture and aims to lower latency by processing data closer to its source.
ASIT provides best training on "Object Oriented Programming" Course , invites lot of people with technical back ground and experienced HR from corporate world as a part of pre-placement training, this actually helps us to perform better in our interviews. For more details please visit our website.
This document summarizes the evolution of the RISC-V software ecosystem from 2015 to 2020. It describes how initial ports of key software in 2015, like GCC and Linux, have expanded to include upstream support in most open source software projects today. It outlines remaining priorities like completing support for specifications and filling gaps in programming language and application software support. The document concludes by encouraging continued collaboration to further mature the RISC-V software ecosystem.
Space Codesign at TandemLaunch Lunch & Learn 20150414Gary Dare
Space Codesign 's presentation by Gary Dare to Montreal TandemLaunch hardware-oriented startup incubator (accelerator) on April 14, 2015. This is a more general presentation on electronics design technology and history of the EDA industry which originated as startups around 1980. Not a product pitch but highlights of SpaceStudio innovation is included. The intended audience is general rather than just electronics and software engineers, and technical management.
This document describes Space Codesign's ESL hardware/software co-design flow for ARM processor-based FPGAs. It allows designers to explore architecture and perform hardware/software partitioning, simulation and monitoring at a high level in SystemC before generating RTL and prototypes. Key benefits include extensive automation, transparent performance analysis, and no recoding needed between SystemC and VHDL. An example Motion JPEG demo shows the ARM Cortex-A9 core achieving over 700 fps compared to under 100 fps for a MicroBlaze and 250+ fps for a Leon3.
Space Codesign CMC Microsystems Webinar 20150205 unrolledSpace Codesign
Space Codesign Systems provides hardware/software co-design tools to optimize system-on-chip design through rapid virtual prototyping and architectural exploration. Their SpaceStudio tool automates hardware/software partitioning and integration to reduce design time versus traditional sequential workflows. SpaceStudio uses SystemC, TLM, and standard processor/IP models to quickly simulate architectural candidates before code generation for FPGA/ASIC implementation.
This document discusses systems on chip (SoCs) for embedded applications. It begins with an overview of what an embedded SoC is and then discusses intellectual property (IP) cores commonly used in SoCs, such as ARM processors and support modules. The document outlines the typical SoC design flow, including modeling and simulation, physical design, and integration. Examples of commercial SoCs are provided. Challenges in SoC design are discussed, such as increasing complexity, requirements for faster design times, and power management. The use of reusable IP blocks is described as a way to reduce costs and risks in SoC design.
The document discusses software-based verification and firmware development. It summarizes Evatronix's work developing IPs and drivers for hardware/software convergence. It describes building a testbench environment in SystemC to functionally verify IPs using ANSI C tests, which can then be reused from virtual prototyping to FPGA prototypes. The document also outlines developing a USB mass storage firmware in C using various abstraction layers, starting in the verification environment and finishing on an FPGA prototype with few modifications.
This document discusses hardware/software codesign. It introduces codesign concepts and benefits over traditional design processes. Codesign allows concurrent development of hardware and software to optimize design tradeoffs. The document outlines topics on codesign fundamentals, tradeoffs, past approaches, and future directions like multiprocessor system-on-chip applications. Codesign moves parts between software and hardware to improve performance while meeting design constraints like cost, power, and time-to-market.
The document discusses design technology for embedded systems. It covers several key topics:
- There is a tradeoff between hardware and software implementation based on metrics like performance, power, size, and flexibility. Hardware and software design are now viewed together.
- Improving productivity involves automation through synthesis and reuse using predesigned components like processor cores. Verification ensures designs are correct and complete.
- Emulators can simulate systems faster than software simulation by mapping designs to FPGAs. This allows testing in real environments. Intellectual property cores provide predesigned processors and components for reuse.
This document discusses embedded systems and their software. It begins by defining the objectives which are to describe embedded system components, software, programming, and hardware description language. It then covers several topics related to embedded systems including real-time considerations, hardware versus software, microprocessor technology, and trends and future directions. Examples are provided throughout to illustrate concepts like hard real-time, firm real-time, and where to place functionality between hardware and software.
The document discusses choosing the right processor for an application. It covers microprocessors, microcontrollers, DSP processors, FPGAs, CPLDs, hardware design flow, software design flow, and various embedded system design phases like simulation, evaluation and emulation. Key factors in processor selection include development tools, performance, cost, operating systems, hardware tools, peripherals and power consumption. The document also provides resources and websites for embedded system development.
This document is a resume for Brian D. Charron, an ASIC design engineer with over 20 years of experience seeking a new opportunity. It lists his professional strengths such as experience with ASIC implementation, physical layout, timing analysis, signal integrity analysis, and collaboration. It also provides details of his professional experience at Intel, Toshiba, and Digital Equipment Corporation, where he has worked on physical design, packaging, DFT, and simulation of ASICs and SOCs from HDL to GDSII. His education includes a bachelor's degree in computer engineering technology from Northeastern University.
This document provides an overview of system on chip (SoC) design. It discusses that a SoC integrates all components of an electronic system onto a single chip, including digital, analog and radio frequency functions. The SoC design process involves identifying user needs and integrating various intellectual property blocks. It describes the SoC design flow, fundamentals like using soft and hard IP cores, and considerations like architecture strategy and validation. Key aspects covered include SoC architecture, on-chip buses to connect IP cores, and examples of commercial SoCs.
This document discusses application-to-architecture mapping and hardware-software codesign. It describes traditional bottom-up and top-down design methodologies. It then summarizes hardware-software partitioning techniques including integer linear programming and global criticality/local phase approaches. Platform-based design is emerging as a trend, reusing architectures like Texas Instruments' OMAP platform or processor-centric platforms like Tensilica's Xtensa.
RISC-V & SoC Architectural Exploration for AI and ML AcceleratorsRISC-V International
This document discusses architectural exploration for AI and ML accelerators using simulation tools. It notes that current AI/ML applications require custom hardware configurations to achieve performance goals. The Imperas simulation tools allow analyzing performance on different hardware designs by running software on virtual platforms months before RTL implementation. Imperas provides virtual platforms for heterogeneous systems running full operating systems along with detailed analysis, profiling and debugging tools. It also includes a RISC-V reference model that enables developing custom instructions for architectural exploration of AI/ML accelerators.
An embedded system is a microprocessor-based system designed to perform specific tasks and embedded as a component in a larger system. Common application areas include automotive electronics, aircraft electronics, trains, and telecommunications. The key design challenge is to optimize numerous design metrics like unit cost, size, performance, power consumption, and flexibility simultaneously. Common integrated circuit technologies used include full-custom/VLSI, semi-custom ASICs, and programmable logic devices like FPGAs. VHDL and Verilog are hardware description languages used to model and simulate the system at different levels of abstraction from transistors to functional behavior.
This document discusses using DesignWare Virtual Platforms for system level verification of a chip design through software development. It outlines how virtual platforms can model a complete embedded system to allow concurrent software development and hardware-software integration. The results shown indicate that using a virtual platform can accelerate firmware development, find bugs earlier, and reduce post-silicon debug time compared to traditional hardware-focused development.
Cockatrice: A Hardware Design Environment with ElixirHideki Takase
Cockatrice is a hardware design environment that allows designing hardware circuits from Elixir code. It synthesizes Elixir code following the "Zen style" of using enumerations and pipelines to describe dataflow into a hardware description language representation of a dataflow circuit. The synthesis flow analyzes the Elixir code, generates hardware modules from functions, connects them as a dataflow circuit, and outputs the final circuit description along with an interface driver for communication between the generated hardware and a Elixir software application. This allows accelerating parts of Elixir code by offloading processing to customized hardware circuits designed from the Elixir code.
The Cypress PSoC is a programmable “system on chip” device which includes all the functions of a traditional microcontroller, in addition to programmable analog and digital blocks. This combination of resources makes the chip well suited to robotics applications. This will be an introductory talk covering the basic architecture and development tools.
Mirabilis_Design AMD Versal System-Level IP LibraryDeepak Shankar
Mirabilis Design provides the VisualSim Versal Library that enable System Architect and Algorithm Designers to quickly map the signal processing algorithms onto the Versal FPGA and define the Fabric based on the performance. The Versal IP support all the heterogeneous resource.
This document provides an overview of system on chip (SoC) design. It discusses that a SoC integrates all components of an electronic system onto a single chip, and that SoC design involves identifying user needs and integrating various intellectual property blocks. The document then covers SoC fundamentals like the use of soft and hard IP cores, the design flow from specification to fabrication, and strategies for addressing SoC complexity through partitioning, abstraction levels, and reuse of pre-designed components.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
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Space Codesign Systems provides hardware/software co-design tools to optimize system-on-chip design through rapid virtual prototyping and architectural exploration. Their SpaceStudio tool automates hardware/software partitioning and integration to reduce design time versus traditional sequential workflows. SpaceStudio uses SystemC, TLM, and standard processor/IP models to quickly simulate architectural candidates before code generation for FPGA/ASIC implementation.
This document discusses systems on chip (SoCs) for embedded applications. It begins with an overview of what an embedded SoC is and then discusses intellectual property (IP) cores commonly used in SoCs, such as ARM processors and support modules. The document outlines the typical SoC design flow, including modeling and simulation, physical design, and integration. Examples of commercial SoCs are provided. Challenges in SoC design are discussed, such as increasing complexity, requirements for faster design times, and power management. The use of reusable IP blocks is described as a way to reduce costs and risks in SoC design.
The document discusses software-based verification and firmware development. It summarizes Evatronix's work developing IPs and drivers for hardware/software convergence. It describes building a testbench environment in SystemC to functionally verify IPs using ANSI C tests, which can then be reused from virtual prototyping to FPGA prototypes. The document also outlines developing a USB mass storage firmware in C using various abstraction layers, starting in the verification environment and finishing on an FPGA prototype with few modifications.
This document discusses hardware/software codesign. It introduces codesign concepts and benefits over traditional design processes. Codesign allows concurrent development of hardware and software to optimize design tradeoffs. The document outlines topics on codesign fundamentals, tradeoffs, past approaches, and future directions like multiprocessor system-on-chip applications. Codesign moves parts between software and hardware to improve performance while meeting design constraints like cost, power, and time-to-market.
The document discusses design technology for embedded systems. It covers several key topics:
- There is a tradeoff between hardware and software implementation based on metrics like performance, power, size, and flexibility. Hardware and software design are now viewed together.
- Improving productivity involves automation through synthesis and reuse using predesigned components like processor cores. Verification ensures designs are correct and complete.
- Emulators can simulate systems faster than software simulation by mapping designs to FPGAs. This allows testing in real environments. Intellectual property cores provide predesigned processors and components for reuse.
This document discusses embedded systems and their software. It begins by defining the objectives which are to describe embedded system components, software, programming, and hardware description language. It then covers several topics related to embedded systems including real-time considerations, hardware versus software, microprocessor technology, and trends and future directions. Examples are provided throughout to illustrate concepts like hard real-time, firm real-time, and where to place functionality between hardware and software.
The document discusses choosing the right processor for an application. It covers microprocessors, microcontrollers, DSP processors, FPGAs, CPLDs, hardware design flow, software design flow, and various embedded system design phases like simulation, evaluation and emulation. Key factors in processor selection include development tools, performance, cost, operating systems, hardware tools, peripherals and power consumption. The document also provides resources and websites for embedded system development.
This document is a resume for Brian D. Charron, an ASIC design engineer with over 20 years of experience seeking a new opportunity. It lists his professional strengths such as experience with ASIC implementation, physical layout, timing analysis, signal integrity analysis, and collaboration. It also provides details of his professional experience at Intel, Toshiba, and Digital Equipment Corporation, where he has worked on physical design, packaging, DFT, and simulation of ASICs and SOCs from HDL to GDSII. His education includes a bachelor's degree in computer engineering technology from Northeastern University.
This document provides an overview of system on chip (SoC) design. It discusses that a SoC integrates all components of an electronic system onto a single chip, including digital, analog and radio frequency functions. The SoC design process involves identifying user needs and integrating various intellectual property blocks. It describes the SoC design flow, fundamentals like using soft and hard IP cores, and considerations like architecture strategy and validation. Key aspects covered include SoC architecture, on-chip buses to connect IP cores, and examples of commercial SoCs.
This document discusses application-to-architecture mapping and hardware-software codesign. It describes traditional bottom-up and top-down design methodologies. It then summarizes hardware-software partitioning techniques including integer linear programming and global criticality/local phase approaches. Platform-based design is emerging as a trend, reusing architectures like Texas Instruments' OMAP platform or processor-centric platforms like Tensilica's Xtensa.
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An embedded system is a microprocessor-based system designed to perform specific tasks and embedded as a component in a larger system. Common application areas include automotive electronics, aircraft electronics, trains, and telecommunications. The key design challenge is to optimize numerous design metrics like unit cost, size, performance, power consumption, and flexibility simultaneously. Common integrated circuit technologies used include full-custom/VLSI, semi-custom ASICs, and programmable logic devices like FPGAs. VHDL and Verilog are hardware description languages used to model and simulate the system at different levels of abstraction from transistors to functional behavior.
This document discusses using DesignWare Virtual Platforms for system level verification of a chip design through software development. It outlines how virtual platforms can model a complete embedded system to allow concurrent software development and hardware-software integration. The results shown indicate that using a virtual platform can accelerate firmware development, find bugs earlier, and reduce post-silicon debug time compared to traditional hardware-focused development.
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The Cypress PSoC is a programmable “system on chip” device which includes all the functions of a traditional microcontroller, in addition to programmable analog and digital blocks. This combination of resources makes the chip well suited to robotics applications. This will be an introductory talk covering the basic architecture and development tools.
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This document provides an overview of system on chip (SoC) design. It discusses that a SoC integrates all components of an electronic system onto a single chip, and that SoC design involves identifying user needs and integrating various intellectual property blocks. The document then covers SoC fundamentals like the use of soft and hard IP cores, the design flow from specification to fabrication, and strategies for addressing SoC complexity through partitioning, abstraction levels, and reuse of pre-designed components.
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1. Space Codesign Systems Inc.
ESL and HW/SW Co-design for Rapid Development of
ARM-based SoC Embedded Systems
ARM Technology Symposium Japan
October 30, 2014
2. Value Proposition
ARM Technology Symposium Japan - October 30, 2014 2
Design Optimization, Increase Productivity, Improve/Maintain Quality
Electronics design is dealing with
larger, more complex systems of
Hardware and Software
Development approaching/exceeds
Product life
Design Changes/Errors are Costly
TI: Silicon Re-spin Costs up to $3
Million (ref. Synopsys Newsletter)
Costly in Time Late to Market!
3. Space Codesign’s SpaceStudio
ARM Technology Symposium Japan - October 30, 2014 3
Next Generation ESL Design Technology
Algorithm / Functional Specification
- Requirements for System Architecture
Architectural Design Exploration
- Hardware/Software Co-design
- Automation supports HW/SW
Partitioning
- Development of System Architecture
Implementation
Focus on System Architects
4. Traditional HW-Centric Workflow
ARM Technology Symposium Japan - October 30, 2014 4
Methodology Impacts Product Development Cycle Time
• Hardware and Software developed on separate paths
• Long design exploration cycles late problem discovery
• Long HW Prototype debug (FPGA, Emulation, etc.)
• Virtual Prototyping has improved speed but not approach
• Risks in Integration Problems prolong time-to-market
Mapped
architecture
Analysis
&
diagnostics
time
HW
architecture
C/C++
application
Weeks!
Integration
SW Devel.
HW Design
5. Henry Ford on Customers’ Needs
ARM Technology Symposium Japan - October 30, 2014 5
Process Improvement Also Needed
If I had asked people what they wanted,
they would have said faster horses.
6. SpaceStudio Agile Workflow
ARM Technology Symposium Japan - October 30, 2014 6
Methodology Improvement Enabled By Next Generation ESL Technology
• Automated transformation of functions between HW and SW
• Reuse the Same Model … Without Recoding
• Fast High Level Simulation Rapid Virtual Prototyping & Analysis
• Agile Work Flow Immediate Integration and Problem Detection
• Rapid Design Exploration Enabled!
time
Mapped
architecture
Analysis
&
diagnostics
HW architecture
with
SystemC TLM
layer
Multi-threaded
C/C++
application Minutes/Hours!
SW, HW,
Firmware
Generation
Integration
7. Modeling Levels and Performance
ARM Technology Symposium Japan - October 30, 2014 7
Abstraction Impact
TimingDetail
Execution
(Simulation) Time
FAST
Untimed
RTL
Loosely
Timed
Approx.
Timed
Slow
FPGA
(Prototype)
Functional
Specification
(Algorithm)
Architecture
Exploration (HW/SW)
Implementation
Cycle
Accurate
Less
More
8. Processor ISS: ARM
ARM Technology Symposium Japan - October 30, 2014 8
ARM Fast Models and QEMU options supported
SpaceStudio supports ARM Cortex-A9 dual core
• Popular wireless core (Apple, Samsung, Nvidia, etc.)
• Choice for new generation of powerful Programmable
Devices (Xilinx Zynq All Programmable SoC, Altera SoC
FPGA)
ARM Fast Models selected for ARM ISS source by Space
Codesign
• Functionally Accurate, High Performance
• Validated by ARM
• Configured with SystemC TLM-2.0 interface
QEMU recently added (ARM, etc.)
9. SpaceStudio Advantages and Benefits
ARM Technology Symposium Japan - October 30, 2014 9
Enabling Reduced Cycle Time
Rapid System Design
• Faster Design Technology (ESL)
• Faster Design Methodology (HW/SW Co-design)
Enabled by Retargeting same model to HW or SW
Performance Analysis
• Faster Feedback on Performance QoR
Power and Silicon Estimation
• Interfaces Industry Standard Tech (e.g., Xilinx 14.4)
FPGA Implementation
• Down to Chip
• Physical Prototype or Final Release
• ASIC development: guided by Virtual Prototype
10. Automation supports HW/SW Partitioning
ARM Technology Symposium Japan - October 30, 2014 10
Same Functions are Retargeted for HW or SW
Drag + Drop
Configuration 1: All SW Configuration 2:
All SW minus IDCT
Drag and Drop Mechanism Eases Design Iteration
Iteration
Task
Coprocessor
11. Hardware/Software Co-Debugging
ARM Technology Symposium Japan - October 30, 2014 11
Simultaneous Debugging without Restart of Hardware Simulation
Software Debuggers + Hardware Debugger
• Communication via Sockets
• Single Environment, Simultaneous Debugging
12. Space Codesign Implementation Flow
ARM Technology Symposium Japan - October 30, 2014 12
Design Creation from Algorithm to Architecture to Implementation
Elix GenX
Functional
(algorithm)
Implementation
SpaceStudio
Architectural
(design exploration,
hw/sw co-design)
….
C/C++
Specifica
tion
Simtek
SoC Virtual
Platform
CPU Core Models (ISS)
IP Reuse
(Mapping)
High Level
Synthesis
Silicon SoC
SoftwareGeneration
13. Space Codesign in Xilinx Vivado Flow
ARM Technology Symposium Japan - October 30, 2014 13
Design Creation Front-End for Xilinx Vivado (including Vivado HLS)
Elix GenX
IP
(EDK/ISE)
Synthesis
(Vivado HLS)
Xilinx FPGA
Functional
(algorithm)
Implementation
SpaceStudio
Architectural
(design exploration,
hw/sw co-design)
SoftwareGeneration
….
C/C++
Specifica
tion
Simtek
Xilinx Virtual
Platform
CPU Core Models (ISS)
14. Space Codesign Ecosystem
ARM Technology Symposium Japan - October 30, 2014 14
Making use of Industry Standards and Leading Technologies
Processor Models
• QEMU (Intel, ARM, PPC, etc.)
• ARM Fast Models (Cortex-A9 dual core)
OS
Standards
HLS Tools
FPGA
SystemC, TLM-2.0 (IEEE 1666)
IP-XACT (IEEE 1685)