Uploaded byGary Dare
Dac49 armcc space_booth
This document describes Space Codesign's ESL hardware/software co-design flow for ARM processor-based FPGAs. It allows designers to explore architecture and perform hardware/software partitioning, simulation and monitoring at a high level in SystemC before generating RTL and prototypes. Key benefits include extensive automation, transparent performance analysis, and no recoding needed between SystemC and VHDL. An example Motion JPEG demo shows the ARM Cortex-A9 core achieving over 700 fps compared to under 100 fps for a MicroBlaze and 250+ fps for a Leon3.
Dac49 armcc space_booth
- 1. Space Codesign ESL Hardware/SoftwareCo-design For ARM Processor-based FPGA Guy Bois – President Laurent Moss – CTO Gary Dare – GM www.spacecodesign.com
- 2. SpaceStudio ESL FlowArchitecture Analysis, H/Scosim & Diagnostics SwSynthesis System Integration Prototype Low Level (Back end) COVERED BY SPACE CODESIGN COVERED BY THIRD PARTIES Applications (C/C++ Code) Interface Synthesis SystemCTLM layers for HW RTOS layers for SW IP Integration Mapping C/C++ SCDrivers High Level (Front end) Application is examined at functional/specification level (algorithm) - C/C++/SystemC Architecture then selected - Impacts Applications, RTOS and IP choice Design exploration - mapping, analysis, iteration Implementation - SW compile, Drivers and HW Synthesis Prototype/Fab ESLFlowRTLFlow mins mins mins 2 Hardware Synthesis
- 3. BenefitsArchitecture Analysis, H/S cosim & Diagnostics SwSynthesis System Integration Prototype LowLevel (Back end) COVERED BY SPACE CODESIGN COVERED BY THIRD PARTIES Applications (C/C++ Code) Interface Synthesis SystemCTLM layers for HW RTOS layers for SW IP Integration Mapping C/C++ SCDrivers High Level (Front end) Extensive automation: • Mapping iterations takes minutes no matter the direction • HW/HW, SW/SW, HW/SW • Fully transparent non- intrusive monitoring for performance analysis • No recoding from SystemC to VHDL is needed • Firmware is automatically generated ESLFlowRTLFlow mins mins mins 3 Hardware Synthesis
- 4. 4 Our Solution Idea/Concept Architecture Exploration and H/SCodesign Algorithm and Functional Specification Physical Implementation / Prototype, Product HW/SW Partitioning, Simulation and Monitoring IP importRTL Generation Elix Gen-X CAD Development Environment SpaceSpace StudioStudio Simtek
- 5. 5 ISS: ARM Cortex-A9Dual MPCore ISS – Instruction Set Simulator Simulation model of CPU that processes instruction code SpaceStudio supports ARM Cortex-A9 Dual MPCore ARM Cortex-A9 is a popular wireless core (used by Apple, Samsung, Nvidia, etc.) ARM Cortex-A9 is the choice for new generation of powerful system FPGA’s (Xilinx Zynq-7000, Altera SoC FPGA) ARM Fast Models selected for ARM ISS source by Space Codesign Functionally Accurate, High Performance, Validated by ARM Configured with SystemC TLM-2.0 interface
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- 7. 7 MJPEG Comparative Performance 5uBlaze 5 Leon3 1 ARM Cortex-A9 0.09673222 0.034892081 0.25233707 MJPEG Decoding of 25 frames < 100 fps 250+ fps 700+ fps