The document describes several digital and analog layout projects completed using Cadence tools including Virtuoso Layout Editor and Assura Verification. For digital projects, standard cells like inverters and logic gates were designed using a 130nm TSMC process. Analog projects included a level shifter, operational amplifier, band gap reference, DAC, and PLL. Challenges involved routing with tight metal pitches, transistor matching, reducing parasitics, and separating analog and digital blocks to prevent noise transfer.

1. DIGITAL LAYOUT PROJECT:
Layout Project : Design of Standard Cell Layout
Tools : Cadence Virtuoso Layout Editor, Assura Verification
Cells Designed : Inverter, NAND, OR, Multiplexer, EX-OR
Technology : TSMC 130nm
Role : Developing layout from Schematic, Spice netlist and verifying
DRC and LVS.
Challenges : Routing using single metal layer by following metal pitch’s and
half DRC rules, Optimization of cell in terms of area power and
time.
ANALOG LAYOUT PROJECT:
Tools : Cadence Virtuoso Layout Editor and Cadence Physical
verification system
Technology : GPDK 45nm
Role : Developing layout from Schematic and verifying DRC and
LVS.
Layout Project 1 : Level shifter
Operation : Level Shifter cell is used to shift a signal voltage range from
one voltage domain to another. It is required when the chip is operating at multiple voltage
domains.
Challenges : Separation of Analog and Digital block using sxcut layer to
avoid noise transfer between them and precise routing for area optimization.
Layout Project 2 : Operational amplifier
Operation : An operational amplifier (or an op-amp) is an integrated circuit
(IC) that operates as a voltage amplifier. It has a differential input. That is, it has two inputs
of opposite polarity. It has a single output and a very high gain, which means that the output
signal is much higher than input signal.
Challenges : Floor planning to get smooth current flow throughout the
circuit, transistor matching, placing Guard ring around critical blocks and reducing parasitics
to meet designer’s requirement.
Layout Project 3 : Band Gap Reference
Operation : A bandgap voltage reference is a temperature independent
voltage reference circuit widely used in integrated circuits. It produces a fixed (constant)

2. voltage regardless of power supply variations, temperature changes and circuit loading from a
device.
Challenges : Floor planning, Resistor matching, BJT matching, adding
dummies properly to avoid STI effect and maintaining EM rules
Layout Project 4 : DAC (Digital to Analog Converter)
Operation : DAC is a device used to convert digital signal into analog
signal based on R-2R ladder network and the switches.
Challenges : R-2R ladder network matching, following EM rules for given
current ratings throughout the circuit, Hierarchical Design and maintaining equal and shortest
routing between each switch and R-2R ladder for reliable output.
Layout Project 5 : PLL (Phase Locked Loop)
Operation : A phase-locked loop (PLL) is an electronic circuit with a voltage or
voltage-driven oscillator that constantly adjusts to match the frequency of an input signal. PLLs are
used to generate, stabilize, modulate, demodulate, filter or recover a signal from a "noisy"
communications channel where data has been interrupted
Challenges : Floor planning according to the size of inductor such that
smooth current flows with optimized area, VCO matching, shielding critical nets,
Maintaining less parasitic and reducing STI and EMI effects