Distributed Generation (DG) System is a small scale electric power generation at or near the user’s facility as
opposed to the normal mode of centralized power generation. In order to ensure safe and reliable operation of
power system based on DS, grid synchronization algorithm plays a very important role. This paper presents a
Double Synchronous Reference Frame (DSRF) phase locked loop (PLL) based on synthesis circuit for grid
synchronization of distributed generation (DG) system under grid disturbances aimed to provide an estimation
of the angular frequency and both the positive and negative sequences of the fundamental component of an
unbalanced three-phase signal. The design of this PLL is based on a complete description of the source voltage
involving both positive and negative sequences in stationary coordinates and considering the angular frequency
as an uncertain parameter.
The document describes a project report on three phase fault analysis with auto reset. It includes a block diagram of the project, descriptions of the hardware components used including transformers, voltage regulators, 555 timers, and relays. It also includes schematic and layout diagrams and details on testing the hardware. The system is designed to automatically disconnect the three phase power supply in the event of a fault, with the supply automatically resetting for temporary faults but remaining tripped for permanent faults.
Fault analysis on three phase system by auto reclosing mechanismeSAT Journals
The document discusses fault analysis on a three phase power system using an auto-reclosing mechanism. It describes different types of faults that can occur such as line-to-ground, line-to-line, and three phase faults. The auto-reclosing mechanism uses a timer IC to open the circuit breaker during a fault and then reclose it after a short delay if the fault is temporary, or keep it open for permanent faults. Simulation results show the mechanism can distinguish between temporary and permanent faults for different fault scenarios. The auto-reclosing helps reduce outage time due to temporary faults and maintain power supply continuity.
Three Phase Fault Analysis With Auto Reset On Temporary Fault And Permanent TripEdgefxkits & Solutions
This PPT explains about Three phase fault analysis. This is achieved by using star to delta conversions.
Edgefxkits.com has a wide range of electronic projects ideas that are primarily helpful for ECE, EEE and EIE students and the ideas can be applied for real life purposes as well.
http://www.edgefxkits.com/
Visit our page to get more ideas on popular electronic projects developed by professionals.
Edgefx provides free verified electronic projects kits around the world with abstracts, circuit diagrams, and free electronic software. We provide guidance manual for Do It Yourself Kits (DIY) with the modules at best price along with free shipping.
three phase auto loadshed phase shift systemtalhawaqar
This three sentence summary provides the key details about the project report:
The project report describes a three phase auto conversion system that detects when a phase loses power and uses a microcontroller to automatically reroute power from another active phase to maintain power delivery. It uses current sensing circuits, relays controlled by a microcontroller, and fuses for overcurrent protection. The system was simulated in Proteus and a PCB was designed to automatically switch phases without interruption of power when one phase fails.
circuit explanation of Three phase fault analysis with auto reset for tempora...Vikram Rawani
this file consisting of the explanation of the circuit diagram in Three phase fault analysis with auto reset for temporary fault and trip for permanent fault.
ppt of Three phase fault analysis with auto reset for temporary fault and tri...Vikram Rawani
it's the final ppt which we have made for the project hope you will like it and make use most of it. it will definitely help you guys .
all the best (Y) :)
This document describes a circuit that automatically selects any available phase from a 3 phase power supply system if one phase fails. It uses transformers connected to each phase, rectifiers, regulators, optoisolators, AND gates, inverters, a relay driver, and relays. When one phase fails, the circuit uses logic gates to switch the load to the next available phase through the relay contacts, ensuring continuous power to single phase loads.
This circuit protects three-phase appliances by monitoring the availability of each phase (R, Y, B). If any phase fails, relays RL1 and RL2 detect this and prevent timer IC1 from triggering. If all phases are available, IC1 triggers after a delay, closing contactor RL4 to supply power to the appliance. When power is interrupted to any phase, it switches off the appliance until all three phases are restored, to avoid damage from fluctuations. LEDs indicate the availability of each individual phase.
The document describes a project report on three phase fault analysis with auto reset. It includes a block diagram of the project, descriptions of the hardware components used including transformers, voltage regulators, 555 timers, and relays. It also includes schematic and layout diagrams and details on testing the hardware. The system is designed to automatically disconnect the three phase power supply in the event of a fault, with the supply automatically resetting for temporary faults but remaining tripped for permanent faults.
Fault analysis on three phase system by auto reclosing mechanismeSAT Journals
The document discusses fault analysis on a three phase power system using an auto-reclosing mechanism. It describes different types of faults that can occur such as line-to-ground, line-to-line, and three phase faults. The auto-reclosing mechanism uses a timer IC to open the circuit breaker during a fault and then reclose it after a short delay if the fault is temporary, or keep it open for permanent faults. Simulation results show the mechanism can distinguish between temporary and permanent faults for different fault scenarios. The auto-reclosing helps reduce outage time due to temporary faults and maintain power supply continuity.
Three Phase Fault Analysis With Auto Reset On Temporary Fault And Permanent TripEdgefxkits & Solutions
This PPT explains about Three phase fault analysis. This is achieved by using star to delta conversions.
Edgefxkits.com has a wide range of electronic projects ideas that are primarily helpful for ECE, EEE and EIE students and the ideas can be applied for real life purposes as well.
http://www.edgefxkits.com/
Visit our page to get more ideas on popular electronic projects developed by professionals.
Edgefx provides free verified electronic projects kits around the world with abstracts, circuit diagrams, and free electronic software. We provide guidance manual for Do It Yourself Kits (DIY) with the modules at best price along with free shipping.
three phase auto loadshed phase shift systemtalhawaqar
This three sentence summary provides the key details about the project report:
The project report describes a three phase auto conversion system that detects when a phase loses power and uses a microcontroller to automatically reroute power from another active phase to maintain power delivery. It uses current sensing circuits, relays controlled by a microcontroller, and fuses for overcurrent protection. The system was simulated in Proteus and a PCB was designed to automatically switch phases without interruption of power when one phase fails.
circuit explanation of Three phase fault analysis with auto reset for tempora...Vikram Rawani
this file consisting of the explanation of the circuit diagram in Three phase fault analysis with auto reset for temporary fault and trip for permanent fault.
ppt of Three phase fault analysis with auto reset for temporary fault and tri...Vikram Rawani
it's the final ppt which we have made for the project hope you will like it and make use most of it. it will definitely help you guys .
all the best (Y) :)
This document describes a circuit that automatically selects any available phase from a 3 phase power supply system if one phase fails. It uses transformers connected to each phase, rectifiers, regulators, optoisolators, AND gates, inverters, a relay driver, and relays. When one phase fails, the circuit uses logic gates to switch the load to the next available phase through the relay contacts, ensuring continuous power to single phase loads.
This circuit protects three-phase appliances by monitoring the availability of each phase (R, Y, B). If any phase fails, relays RL1 and RL2 detect this and prevent timer IC1 from triggering. If all phases are available, IC1 triggers after a delay, closing contactor RL4 to supply power to the appliance. When power is interrupted to any phase, it switches off the appliance until all three phases are restored, to avoid damage from fluctuations. LEDs indicate the availability of each individual phase.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Multilevel inverter fault detectiion classification and diagnosissuryakant tripathi
This document discusses multilevel inverter fault detection, classification and diagnosis. It provides an introduction to multilevel inverters, including their topologies like cascaded H-bridge, flying capacitor, and diode-clamped inverters. It also discusses fault types in multilevel inverters like switch faults and phase faults. Neural networks are proposed for fault identification and diagnosis by analyzing output waveforms and THD values. The document reviews previous work on multilevel inverter topologies, modulation techniques, and applications.
This document summarizes a student project report on analyzing a flyback converter. The project involved designing a simulation circuit for a flyback converter with an input of 12V DC and output of 240V DC. The report includes chapters on the operating principle, simulation, results, and conclusions. The key findings were that the flyback converter was able to step up the input voltage to the desired output level, and the output voltage, current, and input voltage waveforms were obtained through simulation as desired. The switching element used was a MOSFET due to its high power rating and switching speed.
SEMINAR TOPIC- 3 PHASE SELETOR AND PREVENTER FOR INDUSTRIAL APPS. 2007.pptSUJAY RAVI KALE
This document describes a three phase selector and preventer for industrial appliances. It discusses the need for such a device to drive three phase loads from single phase power and protect appliances from phase failures. The project aims to generate three phase power from single phase using a microcontroller and generate PWM output to allow frequency control from 10-100Hz for speed control of induction motors. Main components include a regulated power supply, DIP switches, microcontroller, opto-isolators, signal amplifiers, inverter circuitry, and gate drive power supply.
The document describes a digital phase selector project that was presented. It automatically selects the available power phase line when one fails to prevent equipment damage from a manual changeover. The circuit uses phase sensing, control logic and a relay driver. It prioritizes power phases in the order of R, Y, B, and then inverter backup. When a phase is detected, the control logic activates the corresponding relay to switch the load to that line.
Synchronization of single phase power converters to gridSyed Lateef
1. The document discusses synchronization of single-phase power converters to the electric grid. Grid synchronization is important as more renewable energy sources connect directly to local distribution grids.
2. There are two main grid synchronization methods - frequency-domain detection and time-domain detection. Phase-locked loops (PLLs) are commonly used for time-domain detection.
3. The basic structure of a PLL contains a phase detector, loop filter, and voltage-controlled oscillator. An in-quadrature signal is needed at the phase detector input to eliminate double-frequency oscillations in the phase error signal.
This document describes an automatic phase changer circuit that can shift the load to an alternate power phase if the voltage drops below a certain level in one of the phases. The circuit uses three identical sets that each correspond to one of the three phases (R, Y, B). Each set includes a transformer, comparator, transistor and relay. The transformer steps down the voltage which is then rectified and used as input for the comparator. The comparator compares this voltage to a reference voltage and triggers the transistor and relay if the phase voltage is low, shifting the load to another phase with sufficient voltage. This automatic switching prevents equipment downtime if one phase loses power.
Research on hybrid modulation strategies on the hybridBalamurugan Ramu
This document describes a student project on researching hybrid modulation strategies for multilevel inverters with an H-bridge topology. The project is guided by Mr. C.R. Balamurugan and involves group members S. Amanullah, R. Balamurugan, A. Manivasagan, and M. Sai Natarajan. The objectives are to perform hybrid modulation techniques in MATLAB and choose the most efficient for hardware implementation. Simulation and analysis of different modulation methods are conducted considering total harmonic distortion, voltage, and load conditions like resistive, RL, and induction motor. Hardware implementation involves an FPGA module to generate switching pulses and an H-bridge module using MOSFETs.
IC555 Timer, Monostable and Astable modes of operation; voltage regulators - fixed voltage regulators, adjustable voltage regulators - switching regulators.
This circuit automatically changes the power supply phase to deliver correct voltage when only one phase has the proper voltage. It uses relays to disconnect the load from the low voltage phase and connect it to another phase with higher voltage. When the voltage of the initial phase drops below 200V, a comparator switches on a transistor that energizes a relay. This disconnects the load from that phase and connects it to a different phase through another relay, providing power from the phase with sufficient voltage. It allows equipment to operate even when only one phase in a building has the correct voltage level.
AUTOMATIC ACTIVE PHASE SELECTOR FOR SINGLE ...MAHESH294
This document describes an automatic active phase selector system for single phase loads from a three phase supply. The system monitors the voltage levels of each phase and connects the load to the phase with the highest voltage to provide uninterrupted power. It uses a microcontroller to continuously check phase voltages and control a relay to connect the load to the optimal phase. The system allows single phase equipment to operate reliably even if one or two phases experience outages or low voltage.
Linear Integrated Circuits and Its Applications Unit-V Special ICsSatheeshCS2
Linear Integrated Circuits and Its Applications
Unit-V Special ICs
Mr. C.S.SATHEESH, M.E.(Control Systems),
Assistant Professor, Department of EEE, Muthayammal Engineering College, (Autonomous) Namakkal (Dt), Rasipuram – 637408
Short circuit (wic) testing and parameters.Mustafa Ismail
This document summarizes the topics to be covered in a presentation on short circuit (WIC) testing and parameters for IEEE-IAS. It defines key terms related to short circuits like peak current, total energy, power factor, and current limiting. It also defines types of faults, protections, breaker curves, testing parameters and criteria according to standards. The document emphasizes that workmanship and selective coordination are important to prevent faults and equipment damage from short circuits. Arc flash safety and PPE requirements are also discussed.
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This document provides guidelines for overcurrent protection and coordination settings for industrial equipment such as transformers, buses, feeders, and motors above 600V. It outlines typical recommended pickup and time delay settings as rules of thumb for phase and ground overcurrent relays protecting this equipment. Care must be taken to properly coordinate settings between protective devices to prevent unintended tripping and ensure equipment is protected against damage from faults.
This document describes the design of a DC/DC flyback converter project. It details the initial specifications of the converter including an input voltage of 10V DC and adjustable output voltage range of 5-15V DC. It outlines the preliminary calculations done to determine component values for the open-loop design. Simulation results are presented showing the converter can operate in buck and boost modes. The design of the closed-loop controller using a type 2K compensator is described and simulation waveforms are shown verifying stable voltage regulation. Hardware test plans are laid out to characterize the open-loop and closed-loop performance of the built converter.
FSK , FM DEMODULATOR & VOLTAGE REGULATOR ICS
Application of PLL in FSK & FM demodulation three terminal regulator ics.
Adjustable output voltage regulator LM 317, LM 337 & LM 340 series power supply ics.
Basic design considerations for designed regulated power supply
Cascaded h bridge multilevel inverter for induction motor driveseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document discusses an automatic phase selector (DPS) device that can automatically switch the power supply to loads from available phases. It senses which phase has power and switches the relay contacts to provide power from that phase to prevent interruptions. It is useful in developing countries with unstable power and prevents damage or losses from manual switching. The DPS has a phase sensing block, control logic block to decide phase priority, and relay driver block to control the relay. It can switch single phase loads and is compact, economical, and avoids mechanical contacts. It has applications in apartments, emergencies, industries, offices, malls, and engineering colleges.
Five Level Hybrid Cascaded Multilevel Inverter Harmonic Reduced in PWM Switch...ijsrd.com
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as a inverter. This paper describes a harmonics reduced in a hybrid cascaded multilevel inverter circuit with pulse width modulation (PWM) scheme. These scheme pulse width modulations in modified method are uses reduce switching device. These methods are a conventional inverter and hybrid inverter combine form. This topology used the combined form of a new five level hybrid cascaded multilevel inverter. The multilevel carrier based pulse width modulation methods are used in this topology five level output voltage wave forms is shown in FFT window MATLABE/SIMULINK is used to simulate the inverter circuit operation and control signals.
This document describes a project to remotely control up to 8 power grids using a mobile phone. Key components include an 8051 microcontroller interfaced with a GSM modem to receive control messages and authenticate user numbers. The microcontroller verifies authentication and controls relays connected to electrical equipment. An EEPROM stores grid positions to prevent data loss during power failures. The system allows remote control of power grids from any location via mobile phone.
This document discusses synchronization failure detection between generators and the power grid using under voltage and over voltage detection. It defines synchronization as minimizing differences in voltage, frequency, and phase angle between a generator and the grid. Detection of synchronization failures is important to prevent issues like islanding where generators become disconnected from the main distribution lines. The document outlines various active and passive methods for detecting failures like impedance measurement, frequency shift, and under/over voltage and frequency protections. These detections are important for safety and to avoid power loss or consumption when failures occur.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Multilevel inverter fault detectiion classification and diagnosissuryakant tripathi
This document discusses multilevel inverter fault detection, classification and diagnosis. It provides an introduction to multilevel inverters, including their topologies like cascaded H-bridge, flying capacitor, and diode-clamped inverters. It also discusses fault types in multilevel inverters like switch faults and phase faults. Neural networks are proposed for fault identification and diagnosis by analyzing output waveforms and THD values. The document reviews previous work on multilevel inverter topologies, modulation techniques, and applications.
This document summarizes a student project report on analyzing a flyback converter. The project involved designing a simulation circuit for a flyback converter with an input of 12V DC and output of 240V DC. The report includes chapters on the operating principle, simulation, results, and conclusions. The key findings were that the flyback converter was able to step up the input voltage to the desired output level, and the output voltage, current, and input voltage waveforms were obtained through simulation as desired. The switching element used was a MOSFET due to its high power rating and switching speed.
SEMINAR TOPIC- 3 PHASE SELETOR AND PREVENTER FOR INDUSTRIAL APPS. 2007.pptSUJAY RAVI KALE
This document describes a three phase selector and preventer for industrial appliances. It discusses the need for such a device to drive three phase loads from single phase power and protect appliances from phase failures. The project aims to generate three phase power from single phase using a microcontroller and generate PWM output to allow frequency control from 10-100Hz for speed control of induction motors. Main components include a regulated power supply, DIP switches, microcontroller, opto-isolators, signal amplifiers, inverter circuitry, and gate drive power supply.
The document describes a digital phase selector project that was presented. It automatically selects the available power phase line when one fails to prevent equipment damage from a manual changeover. The circuit uses phase sensing, control logic and a relay driver. It prioritizes power phases in the order of R, Y, B, and then inverter backup. When a phase is detected, the control logic activates the corresponding relay to switch the load to that line.
Synchronization of single phase power converters to gridSyed Lateef
1. The document discusses synchronization of single-phase power converters to the electric grid. Grid synchronization is important as more renewable energy sources connect directly to local distribution grids.
2. There are two main grid synchronization methods - frequency-domain detection and time-domain detection. Phase-locked loops (PLLs) are commonly used for time-domain detection.
3. The basic structure of a PLL contains a phase detector, loop filter, and voltage-controlled oscillator. An in-quadrature signal is needed at the phase detector input to eliminate double-frequency oscillations in the phase error signal.
This document describes an automatic phase changer circuit that can shift the load to an alternate power phase if the voltage drops below a certain level in one of the phases. The circuit uses three identical sets that each correspond to one of the three phases (R, Y, B). Each set includes a transformer, comparator, transistor and relay. The transformer steps down the voltage which is then rectified and used as input for the comparator. The comparator compares this voltage to a reference voltage and triggers the transistor and relay if the phase voltage is low, shifting the load to another phase with sufficient voltage. This automatic switching prevents equipment downtime if one phase loses power.
Research on hybrid modulation strategies on the hybridBalamurugan Ramu
This document describes a student project on researching hybrid modulation strategies for multilevel inverters with an H-bridge topology. The project is guided by Mr. C.R. Balamurugan and involves group members S. Amanullah, R. Balamurugan, A. Manivasagan, and M. Sai Natarajan. The objectives are to perform hybrid modulation techniques in MATLAB and choose the most efficient for hardware implementation. Simulation and analysis of different modulation methods are conducted considering total harmonic distortion, voltage, and load conditions like resistive, RL, and induction motor. Hardware implementation involves an FPGA module to generate switching pulses and an H-bridge module using MOSFETs.
IC555 Timer, Monostable and Astable modes of operation; voltage regulators - fixed voltage regulators, adjustable voltage regulators - switching regulators.
This circuit automatically changes the power supply phase to deliver correct voltage when only one phase has the proper voltage. It uses relays to disconnect the load from the low voltage phase and connect it to another phase with higher voltage. When the voltage of the initial phase drops below 200V, a comparator switches on a transistor that energizes a relay. This disconnects the load from that phase and connects it to a different phase through another relay, providing power from the phase with sufficient voltage. It allows equipment to operate even when only one phase in a building has the correct voltage level.
AUTOMATIC ACTIVE PHASE SELECTOR FOR SINGLE ...MAHESH294
This document describes an automatic active phase selector system for single phase loads from a three phase supply. The system monitors the voltage levels of each phase and connects the load to the phase with the highest voltage to provide uninterrupted power. It uses a microcontroller to continuously check phase voltages and control a relay to connect the load to the optimal phase. The system allows single phase equipment to operate reliably even if one or two phases experience outages or low voltage.
Linear Integrated Circuits and Its Applications Unit-V Special ICsSatheeshCS2
Linear Integrated Circuits and Its Applications
Unit-V Special ICs
Mr. C.S.SATHEESH, M.E.(Control Systems),
Assistant Professor, Department of EEE, Muthayammal Engineering College, (Autonomous) Namakkal (Dt), Rasipuram – 637408
Short circuit (wic) testing and parameters.Mustafa Ismail
This document summarizes the topics to be covered in a presentation on short circuit (WIC) testing and parameters for IEEE-IAS. It defines key terms related to short circuits like peak current, total energy, power factor, and current limiting. It also defines types of faults, protections, breaker curves, testing parameters and criteria according to standards. The document emphasizes that workmanship and selective coordination are important to prevent faults and equipment damage from short circuits. Arc flash safety and PPE requirements are also discussed.
final Year Projects, Final Year Projects in Chennai, Software Projects, Embedded Projects, Microcontrollers Projects, DSP Projects, VLSI Projects, Matlab Projects, Java Projects, .NET Projects, IEEE Projects, IEEE 2009 Projects, IEEE 2009 Projects, Software, IEEE 2009 Projects, Embedded, Software IEEE 2009 Projects, Embedded IEEE 2009 Projects, Final Year Project Titles, Final Year Project Reports, Final Year Project Review, Robotics Projects, Mechanical Projects, Electrical Projects, Power Electronics Projects, Power System Projects, Model Projects, Java Projects, J2EE Projects, Engineering Projects, Student Projects, Engineering College Projects, MCA Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, Wireless Networks Projects, Network Security Projects, Networking Projects, final year projects, ieee projects, student projects, college projects, ieee projects in chennai, java projects, software ieee projects, embedded ieee projects, "ieee2009projects", "final year projects", "ieee projects", "Engineering Projects", "Final Year Projects in Chennai", "Final year Projects at Chennai", Java Projects, ASP.NET Projects, VB.NET Projects, C# Projects, Visual C++ Projects, Matlab Projects, NS2 Projects, C Projects, Microcontroller Projects, ATMEL Projects, PIC Projects, ARM Projects, DSP Projects, VLSI Projects, FPGA Projects, CPLD Projects, Power Electronics Projects, Electrical Projects, Robotics Projects, Solor Projects, MEMS Projects, J2EE Projects, J2ME Projects, AJAX Projects, Structs Projects, EJB Projects, Real Time Projects, Live Projects, Student Projects, Engineering Projects, MCA Projects, MBA Projects, College Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, M.Sc Projects, Final Year Java Projects, Final Year ASP.NET Projects, Final Year VB.NET Projects, Final Year C# Projects, Final Year Visual C++ Projects, Final Year Matlab Projects, Final Year NS2 Projects, Final Year C Projects, Final Year Microcontroller Projects, Final Year ATMEL Projects, Final Year PIC Projects, Final Year ARM Projects, Final Year DSP Projects, Final Year VLSI Projects, Final Year FPGA Projects, Final Year CPLD Projects, Final Year Power Electronics Projects, Final Year Electrical Projects, Final Year Robotics Projects, Final Year Solor Projects, Final Year MEMS Projects, Final Year J2EE Projects, Final Year J2ME Projects, Final Year AJAX Projects, Final Year Structs Projects, Final Year EJB Projects, Final Year Real Time Projects, Final Year Live Projects, Final Year Student Projects, Final Year Engineering Projects, Final Year MCA Projects, Final Year MBA Projects, Final Year College Projects, Final Year BE Projects, Final Year BTech Projects, Final Year ME Projects, Final Year MTech Projects, Final Year M.Sc Projects, IEEE Java Projects, ASP.NET Projects, VB.NET Projects, C# Projects, Visual C++ Projects, Matlab Projects, NS2 Projects, C Projects, Microcontroller Projects, ATMEL Projects, PIC Projects, ARM Projects, DSP Projects, VLSI Projects, FPGA Projects, CPLD Projects, Power Electronics Projects, Electrical Projects, Robotics Projects, Solor Projects, MEMS Projects, J2EE Projects, J2ME Projects, AJAX Projects, Structs Projects, EJB Projects, Real Time Projects, Live Projects, Student Projects, Engineering Projects, MCA Projects, MBA Projects, College Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, M.Sc Projects, IEEE 2009 Java Projects, IEEE 2009 ASP.NET Projects, IEEE 2009 VB.NET Projects, IEEE 2009 C# Projects, IEEE 2009 Visual C++ Projects, IEEE 2009 Matlab Projects, IEEE 2009 NS2 Projects, IEEE 2009 C Projects, IEEE 2009 Microcontroller Projects, IEEE 2009 ATMEL Projects, IEEE 2009 PIC Projects, IEEE 2009 ARM Projects, IEEE 2009 DSP Projects, IEEE 2009 VLSI Projects, IEEE 2009 FPGA Projects, IEEE 2009 CPLD Projects, IEEE 2009 Power Electronics Projects, IEEE 2009 Electrical Projects, IEEE 2009 Robotics Projects, IEEE 2009 Solor Projects, IEEE 2009 MEMS Projects, IEEE 2009 J2EE P
This document provides guidelines for overcurrent protection and coordination settings for industrial equipment such as transformers, buses, feeders, and motors above 600V. It outlines typical recommended pickup and time delay settings as rules of thumb for phase and ground overcurrent relays protecting this equipment. Care must be taken to properly coordinate settings between protective devices to prevent unintended tripping and ensure equipment is protected against damage from faults.
This document describes the design of a DC/DC flyback converter project. It details the initial specifications of the converter including an input voltage of 10V DC and adjustable output voltage range of 5-15V DC. It outlines the preliminary calculations done to determine component values for the open-loop design. Simulation results are presented showing the converter can operate in buck and boost modes. The design of the closed-loop controller using a type 2K compensator is described and simulation waveforms are shown verifying stable voltage regulation. Hardware test plans are laid out to characterize the open-loop and closed-loop performance of the built converter.
FSK , FM DEMODULATOR & VOLTAGE REGULATOR ICS
Application of PLL in FSK & FM demodulation three terminal regulator ics.
Adjustable output voltage regulator LM 317, LM 337 & LM 340 series power supply ics.
Basic design considerations for designed regulated power supply
Cascaded h bridge multilevel inverter for induction motor driveseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document discusses an automatic phase selector (DPS) device that can automatically switch the power supply to loads from available phases. It senses which phase has power and switches the relay contacts to provide power from that phase to prevent interruptions. It is useful in developing countries with unstable power and prevents damage or losses from manual switching. The DPS has a phase sensing block, control logic block to decide phase priority, and relay driver block to control the relay. It can switch single phase loads and is compact, economical, and avoids mechanical contacts. It has applications in apartments, emergencies, industries, offices, malls, and engineering colleges.
Five Level Hybrid Cascaded Multilevel Inverter Harmonic Reduced in PWM Switch...ijsrd.com
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as a inverter. This paper describes a harmonics reduced in a hybrid cascaded multilevel inverter circuit with pulse width modulation (PWM) scheme. These scheme pulse width modulations in modified method are uses reduce switching device. These methods are a conventional inverter and hybrid inverter combine form. This topology used the combined form of a new five level hybrid cascaded multilevel inverter. The multilevel carrier based pulse width modulation methods are used in this topology five level output voltage wave forms is shown in FFT window MATLABE/SIMULINK is used to simulate the inverter circuit operation and control signals.
This document describes a project to remotely control up to 8 power grids using a mobile phone. Key components include an 8051 microcontroller interfaced with a GSM modem to receive control messages and authenticate user numbers. The microcontroller verifies authentication and controls relays connected to electrical equipment. An EEPROM stores grid positions to prevent data loss during power failures. The system allows remote control of power grids from any location via mobile phone.
This document discusses synchronization failure detection between generators and the power grid using under voltage and over voltage detection. It defines synchronization as minimizing differences in voltage, frequency, and phase angle between a generator and the grid. Detection of synchronization failures is important to prevent issues like islanding where generators become disconnected from the main distribution lines. The document outlines various active and passive methods for detecting failures like impedance measurement, frequency shift, and under/over voltage and frequency protections. These detections are important for safety and to avoid power loss or consumption when failures occur.
Detecting Power Grid Synchronization Failure on Sensing Frequency or Voltage ...Edgefxkits & Solutions
Synchronization means the minimization of difference in voltage, frequency and phase angle between the corresponding phases of the generator output and grid supply. An alternating current generator must be synchronized with the grid prior to connection. It can’t deliver the power unless it is running at same frequency as the network.
DETECTING POWER GRID SYNCHRONISATION FAILURE ON SENSING BAD VOLTAGE OR FREQUENCYPradeep Avanigadda
This paper presents the development of a microcontroller based islanding detection for grid connected inverter with very simple under/over voltage and under/over frequency islanding detection algorithms.
The microcontroller monitors the under/over voltage and under/over frequency from utility grid and the processed value of voltage and frequency for turning ON/OFF the relay between a grid connected inverter and the utility grid.
The project would alternatively use a variable frequency generator using 555timer for changing the frequency while a standard variac shall be used to vary the input voltage for achieving the test conditions as stated above.
This document provides an overview of Indian Oil Corporation Limited (IOCL) and discusses the objective of selecting pumps for their cross-country pipeline system. IOCL is India's largest oil and gas company, with a large refining capacity and extensive retail network. The document discusses the types of pumps used in oil industries, focusing on centrifugal pumps. It explains that the objective is to understand IOCL's pump selection process by examining key pump characteristics like pressure, velocity and head, and how these are used to create characteristic curves and select pumps to keep costs low and efficiency high.
DETECTING POWER GRID SYNCHRONISATION FAILURE ON SENSING BAD VOLTAGE OR FREQUE...Pradeep Avanigadda
The project is designed to develop a system to detect the synchronization failure of any external supply source to the power grid on sensing the abnormalities in frequency and voltage.
There are several power generation units connected to the grid such as hydel, thermal, solar etc to supply power to the load. These generating units need to supply power according to the rules of the grid. These rules involve maintaining a voltage variation within limits and also the frequency. If any deviation from the acceptable limit of the grid it is mandatory that the same feeder should automatically get disconnected from the grid which by effect is termed as islanding. This prevents in large scale brown out or black out of the grid power. So it is preferable to have a system which can warn the grid in advance so that alternate arrangements are kept on standby to avoid complete grid failure.
Enhancement for Power Quality in Distribution Side Using Custom Power DevicesIOSR Journals
1) The document discusses enhancing power quality in distribution systems using custom power devices like the Interline Unified Power Quality Conditioner (IUPQC).
2) It proposes using a Synchronous Reference Frame (SRF) control algorithm with a modified Phase Locked Loop (PLL) for generating gate signals to improve the IUPQC's performance under distorted voltage conditions.
3) The SRF method transforms voltage and current signals into rotating dq coordinates to extract fundamental frequency components, while the modified PLL improves determination of positive sequence system voltages for better filtering.
Symmetrical components in transient regimegaonioni
The document presents an extended zero sequence equivalent circuit model for simulating single line to ground faults in distribution systems. The model improves upon traditional zero sequence models by accounting for the contribution of load currents to the voltage drop, through a correction factor applied to the supply voltage. This provides a more accurate representation of the inception voltage at the fault location. The extended model is able to simulate transient fault regimes more accurately than traditional models. It has also been applied successfully in a fault location algorithm, improving the range of fault resistance and location that can be identified compared to previous methods.
Modified Synchronous Reference Frame based Harmonic Extraction for Shunt Acti...IJPEDS-IAES
This paper presents the modified synchronous reference frame based Shunt
Active Filter (SAF) for the instantaneous compensation of harmonic current
present at the Point of Common Coupling. The harmonics generated by the
non linear load are extracted using the positive frame and negative frame of
the input signal using the modified synchronous reference frame theory with
extended Multiple Reference Frame based PLL (EMRFPLL). Based on the
harmonics extracted, pulse width modulation signals are generated using
Artificial Neural Network based Space Vector Pulse width Modulation
technique (ANNSVPWM). Using this switching technique the losses can be
reduced and compensation can be done more accurately The concept was
verified using MATLAB / Simulink Simulation and the results confirm the
THD at point of common coupling is below the required standards.
Solar Panel Using Active Stacked Npc Multi Level Converterirjes
In this project, the operation and the features of a new three-level converter are presented with PV
source and boost converter. The proposed topology was named three-level active-stacked neutral point clamped.
It is a derivative of the 3L-SNPC structure, having two additional active switches connected anti parallel with
the clamp diodes. The main advantage of 3L-ASNPC converter is the reduction of the average switching
frequency for all power devices. In the same time, the apparent switching frequency of the output voltage is
doubled.
SVM-plus-Phase-Shift Modulation Strategy for Single-Stage.pdfgulie
This document proposes a new modulation strategy called SVM-plus-phase-shift (SVM-PS) modulation for a single-stage three-phase resonant AC-DC matrix converter with an LCL resonant tank. The strategy aims to achieve unity power factor and flexible control of active and reactive power transfer. It derives the relationship between switch states and line-frequency phase currents based on the fundamental component of the tank current. This allows simple control of current amplitude and phase via modulation of the AC and DC side switches based on voltage and current references. Simulation results show the proposed strategy reduces current distortion and ripple compared to conventional SVM.
This document presents an optimized synchronous technique for a single-phase enhanced phase locked loop (EPLL). It compares the performance of a first-order adaptive notch filter (ANF) and a second-order ANF in the EPLL design. Simulation results show that under normal operating conditions and various fault scenarios, the second-order ANF-based PLL provides faster locking, less oscillation in the error signal, and lower integration error values compared to the first-order ANF design. The second-order ANF design demonstrates better immunity and accuracy in phase tracking.
ER Publication,
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Synchronization of Grid Voltage for Solar and Wind Distributive Systems Under...IRJET Journal
This document compares three phase locked loop (PLL) techniques for synchronizing grid voltage under faults: decoupled double synchronous reference frame PLL (DDSRF PLL), dual second order generalized integrator PLL (DSOGI PLL), and three phase enhanced PLL (3ph EPLL). Simulation results show that under faults like three phase faults, line-to-ground faults, and line-to-line faults, all three techniques estimate voltage magnitude and phase within 20-30 milliseconds. However, under polluted grids with harmonics, DDSRF PLL and 3ph EPLL provide better filtering and estimation than DSOGI PLL. Overall, DDSRF PLL and DSOGI PLL offer better performance tradeoffs than
1. The document discusses various methods of FM demodulation including balanced slope detector, Foster-Seeley discriminator, phase locked loop demodulator, and ratio detector.
2. It provides details on the basic principles and circuit operations of each method. The balanced slope detector uses three tuned circuits which makes it difficult to tune. The Foster-Seeley discriminator and ratio detector have better linearity due to their use of phase relationships.
3. The phase locked loop demodulator tracks the instantaneous frequency of the input signal using a voltage controlled oscillator and error signal in a feedback loop. It has good performance even at low signal-to-noise ratios.
Control of Grid- Interfacing Inverters with Integrated Voltage Unbalance Corr...IOSR Journals
This document describes a control scheme for grid-interfacing inverters to correct voltage unbalance at the point of common coupling (POC). It proposes adding a function to intentionally regulate negative sequence currents in order to minimize negative sequence voltage at the POC. The control scheme uses symmetric sequence decomposition with a multi-variable filter to detect positive and negative sequence voltages. It then determines the desired negative sequence current based on the voltage unbalance factor. Experimental results on a laboratory prototype show the inverter is able to reduce the negative sequence voltage at the POC by absorbing a small negative sequence current from the grid.
A phase locked loop (PLL) is a feedback system that uses a voltage controlled oscillator (VCO) and phase comparator to maintain a constant phase angle between a reference signal and the VCO output signal. The basic PLL architecture consists of a phase detector, loop filter, VCO, and feedback divider. Negative feedback forces the phase error signal to approach zero, locking the frequencies. Fractional-N PLLs allow output frequency resolution smaller than the reference signal by varying the modulus of a dual-modulus prescaler. Key specifications for PLL design include lock time, phase noise, reference spurs, and stability.
This document summarizes the results of an indoor channel measurement experiment using USRP boards and GnuRadio. A spread spectrum channel sounder was implemented using a PN sequence transmitted from one USRP and correlated at a receiving USRP. Measurements were taken at different stations in a lab room with LOS and NLOS configurations. The data showed shifting of LOS peaks over time due to unsynchronized clocks between USRPs. With synchronized clocks, distinct multipath components were observable. The experiment demonstrated basic properties of PN sequences and their use in channel sounding.
Comparison of Control Strategies of DSTATACOM for Non-linear Load Compensationidescitation
This document compares five control strategies for a DSTATCOM system used for load compensation: instantaneous p-q theory, synchronous reference frame (SRF) method, modified SRF method, instantaneous symmetrical component theory, and average unit power factor theory. The performance of each control strategy is evaluated through simulations considering the source current total harmonic distortion under different operating conditions. The results show that the modified SRF method has improved system performance compared to the other strategies, especially under deteriorated operating conditions with unbalanced loads or voltage distortions.
THIS PPT IS GIVEN BY EC FINAL YEAR STUDENTS OF BCE-MANDIDEEP TO PROF. RAVITESH MISHRA ON CHARGED PUMP PLLS AS AN ASSIGNMENT FROM RAZAVI,DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS
This document summarizes an adaptive fuzzy logic power filter for nonlinear systems. It proposes using a Takagi-Sugeno fuzzy logic controller (FLC) to control a three-phase shunt active power filter (SAPF) to compensate for harmonic distortion and power quality issues caused by nonlinear loads. The FLC generates reference compensation currents and maintains the SAPF DC capacitor voltage. It is compared to a conventional PI controller, with the FLC showing better robustness to load and system parameter changes. The document describes the instantaneous reactive power theory used to estimate compensation currents, the design of the Takagi-Sugeno FLC, and an adaptive hysteresis current control method to generate switching signals for the SAPF
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The document provides an overview of phase locked loops (PLLs). It discusses:
- The basic components of a PLL including a phase detector, low pass filter, and voltage controlled oscillator (VCO). The phase detector compares the phase difference between an input signal and VCO output.
- Applications of PLLs such as frequency modulation decoding, frequency synthesis, and clock generation.
- Key parameters like lock range, which is the range of input frequencies a PLL can lock onto, and capture range, which is the range a PLL can lock onto when starting unlocked.
- Operation of a basic PLL, including free running, capture, and phase lock stages where the VCO frequency adjusts until matching the
Single-phase transformerless inverter topologies at different levels for a p...IJECEIAES
In this paper, we have studied the topologies of single-phase transformerless inverters with different levels using a proportional-integral-resonant (PIR) AC controller, and the multi-level cascade inverter topology with sinusoidal pulse with modulation (SPWM) control in an open and closed loop. To ensure that these photovoltaic inverters can inject a defined amount of reactive power into the grid according to international regulations. Therefore, precise monitoring of the mains voltage vector by a phase-locked loop (PLL) system is applied to ensure the proper functioning of this system. For inverter topologies with less than three levels, the simulation results show that the highly efficient and reliable inverter concept (HERIC) topology performance is better than that of H5 and H6. On the other hand, the performance of the topology H6 ameliorate is superior to those of H4, H5, and HERIC in currents of leakage. On the other hand, for the control of cascaded multi-level closed-loop inverters, we notice that there is an improvement in the spectra and the elimination of all frequency harmonics, close to that of the fundamental, and a reduction in the rate of harmonic current distortion.
A Distinctive Scheme for Extraction of Symmetrical Components along with Harm...IOSR Journals
1. The document describes a software program developed in C++ Builder to extract symmetrical components and harmonics from three-phase current signals using digital filters.
2. The software was tested on simulated power systems under balanced, unbalanced, fault, and harmonic conditions and was able to satisfactorily extract the symmetrical components and harmonics.
3. Examples are provided to demonstrate the software's ability to extract symmetrical components and harmonics from simulated three-phase systems under various balanced and unbalanced conditions, as well as during different fault scenarios.
Analysis of Multilevel Inverter using Bipolar and Unipolar Switching Schemes ...ijsrd.com
Cascaded H-bridge Multilevel Inverter (MLI) is most efficient topology for medium and high voltage DC-AC conversion, having less output harmonics and less commutation losses. Disadvantages are their complexity, more number of power devices, passive components and a complex control circuitry. Here a Cascaded Hybrid Multilevel Inverter is used to produce a three phase 9-level output voltages. Now a day inverter is also know as a DC-AC converter, is one of the most popular part of electrical device. This proposed inverter widely used in industries application such as speed control of induction motor. This thesis focus on three phase 9-level bipolar and unipolar switching inverter with characteristics like output voltage boosting ability and also we discus about the bipolar and unipolar switching scheme along with capacitor voltage control. The modified topology uses Cascaded H-bridge (CHB) with bidirectional and unidirectional switches producing boost up output voltage. Here a hybrid Pulse Width Modulation (PWM) technique is applied to control the power devices. This modulation technique uses a sine wave and a repeating wave, these waves are combined and a complete reference wave is generated. There is comparative study between CHB and modified topology between number of power devices used and Total Harmonic Distortions (THD). THD of modified topology is reduced and analyzed by FFT window. The results are observed by MATLAB/SIMULINK software.
Similar to Improved Grid Synchronization Algorithm for DG System using DSRF PLL under Grid disturbances (20)
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
A SYSTEMATIC RISK ASSESSMENT APPROACH FOR SECURING THE SMART IRRIGATION SYSTEMSIJNSA Journal
The smart irrigation system represents an innovative approach to optimize water usage in agricultural and landscaping practices. The integration of cutting-edge technologies, including sensors, actuators, and data analysis, empowers this system to provide accurate monitoring and control of irrigation processes by leveraging real-time environmental conditions. The main objective of a smart irrigation system is to optimize water efficiency, minimize expenses, and foster the adoption of sustainable water management methods. This paper conducts a systematic risk assessment by exploring the key components/assets and their functionalities in the smart irrigation system. The crucial role of sensors in gathering data on soil moisture, weather patterns, and plant well-being is emphasized in this system. These sensors enable intelligent decision-making in irrigation scheduling and water distribution, leading to enhanced water efficiency and sustainable water management practices. Actuators enable automated control of irrigation devices, ensuring precise and targeted water delivery to plants. Additionally, the paper addresses the potential threat and vulnerabilities associated with smart irrigation systems. It discusses limitations of the system, such as power constraints and computational capabilities, and calculates the potential security risks. The paper suggests possible risk treatment methods for effective secure system operation. In conclusion, the paper emphasizes the significant benefits of implementing smart irrigation systems, including improved water conservation, increased crop yield, and reduced environmental impact. Additionally, based on the security analysis conducted, the paper recommends the implementation of countermeasures and security approaches to address vulnerabilities and ensure the integrity and reliability of the system. By incorporating these measures, smart irrigation technology can revolutionize water management practices in agriculture, promoting sustainability, resource efficiency, and safeguarding against potential security threats.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
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for future exploration and optimization of advanced CNN models in medical
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TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEMHODECEDSIET
Time Division Multiplexing (TDM) is a method of transmitting multiple signals over a single communication channel by dividing the signal into many segments, each having a very short duration of time. These time slots are then allocated to different data streams, allowing multiple signals to share the same transmission medium efficiently. TDM is widely used in telecommunications and data communication systems.
### How TDM Works
1. **Time Slots Allocation**: The core principle of TDM is to assign distinct time slots to each signal. During each time slot, the respective signal is transmitted, and then the process repeats cyclically. For example, if there are four signals to be transmitted, the TDM cycle will divide time into four slots, each assigned to one signal.
2. **Synchronization**: Synchronization is crucial in TDM systems to ensure that the signals are correctly aligned with their respective time slots. Both the transmitter and receiver must be synchronized to avoid any overlap or loss of data. This synchronization is typically maintained by a clock signal that ensures time slots are accurately aligned.
3. **Frame Structure**: TDM data is organized into frames, where each frame consists of a set of time slots. Each frame is repeated at regular intervals, ensuring continuous transmission of data streams. The frame structure helps in managing the data streams and maintaining the synchronization between the transmitter and receiver.
4. **Multiplexer and Demultiplexer**: At the transmitting end, a multiplexer combines multiple input signals into a single composite signal by assigning each signal to a specific time slot. At the receiving end, a demultiplexer separates the composite signal back into individual signals based on their respective time slots.
### Types of TDM
1. **Synchronous TDM**: In synchronous TDM, time slots are pre-assigned to each signal, regardless of whether the signal has data to transmit or not. This can lead to inefficiencies if some time slots remain empty due to the absence of data.
2. **Asynchronous TDM (or Statistical TDM)**: Asynchronous TDM addresses the inefficiencies of synchronous TDM by allocating time slots dynamically based on the presence of data. Time slots are assigned only when there is data to transmit, which optimizes the use of the communication channel.
### Applications of TDM
- **Telecommunications**: TDM is extensively used in telecommunication systems, such as in T1 and E1 lines, where multiple telephone calls are transmitted over a single line by assigning each call to a specific time slot.
- **Digital Audio and Video Broadcasting**: TDM is used in broadcasting systems to transmit multiple audio or video streams over a single channel, ensuring efficient use of bandwidth.
- **Computer Networks**: TDM is used in network protocols and systems to manage the transmission of data from multiple sources over a single network medium.
### Advantages of TDM
- **Efficient Use of Bandwidth**: TDM all
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
Improved Grid Synchronization Algorithm for DG System using DSRF PLL under Grid disturbances
1. R.Godha et al. Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Version - 4), November 2014, pp.48-54
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Improved Grid Synchronization Algorithm for DG System using DSRF PLL under Grid disturbances R.Godha1 Ch.V.S.S.Sailaja2 K.V.Ramana Murthy3 PG Scholor EEE,VCE Associate Professor EEE,VCE Professor EEE,VCE
Abstract— Distributed Generation (DG) System is a small scale electric power generation at or near the user’s facility as opposed to the normal mode of centralized power generation. In order to ensure safe and reliable operation of power system based on DS, grid synchronization algorithm plays a very important role. This paper presents a Double Synchronous Reference Frame (DSRF) phase locked loop (PLL) based on synthesis circuit for grid synchronization of distributed generation (DG) system under grid disturbances aimed to provide an estimation of the angular frequency and both the positive and negative sequences of the fundamental component of an unbalanced three-phase signal. The design of this PLL is based on a complete description of the source voltage involving both positive and negative sequences in stationary coordinates and considering the angular frequency as an uncertain parameter.
Keywords- Grid synchronization, phase locked loop, power quality, grid disturbances, positive and negative sequence detection, synthesis circuit, adaptive control, frequency estimation.
I. INTRODUCTION
The power generation systems based on renewable energy systems are distributed near the user's facility. These Distributed Generation (DG) systems need to be controlled properly in order to ensure sinusoidal current injection into the grid. However, they have a poor controllability due to their intermittent characteristics [3]. The major issue associated with DG system is their synchronization with utility voltage vector [4]. Henceforth the study of grid synchronization algorithms is essential. Few of the earliest known synchronization algorithms include Zero Crossing Detectors (ZCDs). The performance of ZCDs is badly affected by power quality problems, especially in the case of weak grid. The use of Phase Locked Loops (PLLs) for grid synchronization has shown much better results as discussed in [5]. The Linear PLL is mainly used to detect phase for single phase supply. For balanced three phase supply, Synchronous Reference Frame (SRF) PLL is used. But it is found that this PLL fails to detect the phase for unbalanced supply [6]. Hence Decoupled Double Synchronous Reference Frame (DDSRF) PLL was proposed to deal with unbalanced grid conditions like voltage unbalance [7]. DDSRF PLL can detect the positive sequence phase angle in such conditions. Double Synchronous Reference PLL based on synthesis circuit was proposed in [6] which is more frequency adaptive and can be easily implemented. This paper presents a Double Synchronous Reference Frame (DSRF) PLL (based on synthesis
circuit) for grid synchronization of DG system under grid disturbances. Due to flexible in characteristics, DSRF PLL can accurately detect the phase irrespective of the grid conditions along with decoupling of positive and negative sequence components. Further, it demonstrates how the PLLs can track the phase angle during some of the major abnormal grid conditions like voltage unbalance, line to ground fault and voltage sag etc. The superiority of DSRF PLL over SRF PLL is well illustrated by the simulations results obtained from MATLAB/SIMULINK environment. This paper also presents an algorithm to implement a PLL, which is able to provide an estimation of the angular frequency and both the positive and negative sequences of the fundamental component of an unbalanced three-phase signal. These sequences are provided in fixed -reference- frame coordinates. The synchronization process in the UH-PLL is based on the detection of the fundamental frequency [15]–[17].
II. ANALYSIS OF SRF PLL
A synchronous Reference Frame PLL (SRF PLL) is mainly used for tracking the phase angle in case of 3-phase signals which uses Park’s Transformation of a 3 phase signal as the Phase Detector (PD). Fig.1 depicts the block diagram of a SRF PLL in which va , vb, vc are the components of a 3 phase signal. First block in the Fig.1 is Clarke’s
RESEARCH ARTICLE OPEN ACCESS
2. R.Godha et al. Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 3), November 2014, pp.48-54
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Transformation which translates a three-phase voltage vector from the abc natural reference frame to the αβ stationary reference frame. The second block is the Park’s Transformation which translates the αβ stationary reference frame to rotating frame. A Proportional Integrator (PI) controller is used as loop filter.
Fig.1 Schematic of SRF PLL The SRF PLL can be mathematically described by the following equations [6]:- Under ideal utility conditional, i.e., neither harmonic distortion nor unbalance, the d- and q-axis component can be express by: VdVq cosθ^sinθ^ −sinθ^cosθ^ = U cosθU sinθ = U cos(θ−θ^) U sin(θ−θ^) (1) Where θ and 휃^ represent the phase of input signal and output of PLL respectively; U is the amplitude of input signal,푉푑, 푉푞 are the d- and q-axis component. Under unbalance utility conditions (without voltage harmonics), the voltage vector can be generically expressed as: V = 푉++ 푉− + 푉0 Where subscripts +, – and 0 define the vector for the positive, negative and zero sequence components. Using Clarke’s transformation, the utility voltage vector is given by: Vαβ = U+cosθ+ +U− cosθ− U+ sinθ+ + U− sinθ− (2) By Park’s transformation Vdq = Tdq/αβ Vαβ = U+cos(θ+−휃^)+ U− cos(θ−−휃^) U+ sin(θ+−휃^) + U− sin(θ−−휃^) (3) Where 휔 is the angular frequency of voltage vector and 휃^≈θ+=−θ−=휔푡 in steady state. So if the conventional SRF PLL is used during unbalanced grid conditions the second harmonic ripples are so high that makes it difficult to get the information of phase angle and amplitude.
III. ANALYSIS OF DSRF PLL
From [6] the Dual SRF PLL (DSRF PLL) is a combination of two conventional SRF-PLLs. These two frames are separated by a synthesis circuit. The voltage vector is decomposed into positive and negative sequence vectors and these components are denoted by v+ and v- respectively as shown in Fig. 2. As shown in Fig. 4, the α - and ß-axis components both contain the information of the positive sequence and negative sequence which makes it difficult to detect the positive sequence component. The two PLLs work independently, rotating with positive direction and negative direction respectively and detect the positive sequence and negative sequence simultaneously.
Fig. 2 Voltage Vector Decomposition (unbalanced voltage)
Fig. 3 Synthesis Circuit used in DSRF PLL
Fig. 4 Dual SRF PLL structure
The d-axis component from the Park’s transformation is fed to the synthesis circuit. This signal is actually the voltage amplitude in steady state. The synthesis circuit consists of a Low Pass Filter (L.P.F.), two multipliers, and two orthogonal trigonometric
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functions as shown in Fig. 3. The main objective of the orthogonal functions is to create orthogonal and in-phase signals with respect to the input signal multiplying them with the amplitude. These signals are used as decoupling signals as shown in the Fig. 4. The two PLLs are required to detect the positive and negative sequence at the same time. The signals generated by the synthesis circuit are used as feedback for the unbalanced input signal. The input to the Park’s transformation, Vα and Vβ is the difference of actual Vα and Vβ and the generated signals from the other PLL. As the process goes on the input to the PLL cleans up and the distortion at the output is cancelled. The positive sequence is detected by the PLL with 휔0+as the initial angular frequency and the negative sequence is detected by the one with 휔0−as the initial angular frequency. The behavior of DSRF PLL is explained by the equation given below [6]. In the initial state, 푣푑 is zero, 휃^ is 휔0푡, the output of synthesis circuit are all equal to zero that means decoupling circuit has no effect and each PLLs contains both positive sequence and negative sequence information. In rotating reference frame rotating with positive direction, the Park’s transformation output is: 푉푑+ 푉푞+ = U+ cos(θ+−θ^ +) sin(θ+−θ^ +) + U− cos(θ−−휃^ −) sin(θ−−휃^ −) (4) 휃^ + is 휔0+푡 at initial state, where 휔0+ is approximate the centre angular frequency of positive sequence component. Then (5) becomes Vd+ Vq+ = U++ U− cos −2ω0+t U−sin −2ω0+t (5) There is 2ω ripple including in the d-axis component, so a low-pass filter (LPF) is need to attenuate ripple and help the PLL to get stable. The LPF can be defined as: LPF s = 휔푐 푠+휔푐 Where 휔푐 determines the cut-off frequency of LPF. In order to analyze the behavior of proposed PLL. The state equations can be derived as 푥 1=휔푐(U+−푥1+ (U−−푥2) 푐표푠 θ+−휃− ) 푥 2= 휔푐 (U−−푥2+ (U+−푥1 )푐표푠 θ+−휃− ) (6) Where 푥 1=U+ 푥 2=U−
When the state variables get into steady state, there will be 푥1=U+ and 푥2=U− .That is, the d-axis component will converge to input voltage vector amplitude after some time, and synthesis circuit start to output decoupling signals. At last the input of each PLL will be:
Vα+=Vα −U− cosθ−=U+cosθ+ Vβ+= Vβ− U− sinθ−=U+ sinθ+ (7) And Vα−=Vα −U+ cosθ+=U−cosθ− Vβ−= Vβ− U+ sinθ+=U− sinθ−
IV. RESULTS AND DISCUSSIONS
A. SRF PLL Under Unbalanced Three Phase Voltage
The results obtained from simulation of SRF PLL for unbalanced input voltage are shown in Fig. 5. Fig. 5 (a) shows the 3 phase unbalanced input fed to an SRF PLL such that phase a magnitude is greater than the other 2 phases. As described in (4) the d and q axis voltages are not constant, rather contains second harmonic ripples. Fig. 5 (b) shows these second harmonic components in d axis and q axis voltages. This sinusoidal nature in q axis voltage affects the output of PI controller and generates sinusoidal error signal and hence sinusoidal angular frequency (at central frequency 휔0which is 100 π in this case). From Fig.5 (c), it can be seen that, the detected phase obtained by the time integration of angular frequency is not perfectly triangular but rather contains sinusoidal variations.
(a)
(b)
(c) Fig.5 Simulation Results for SRF PLL under unbalanced grid conditions. (a) grid voltage waveforms (b) d-q components of grid voltage (c) detected phase angle.
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B. Dynamic Response of DSRF PLL Under unbalaced Grid Voltages
The dynamic responses obtained from simulation for DSRF PLL under unbalance input voltage are shown in Fig.6. The PI tuning used for these results are Kp =67.5 and Ki =100.
(a)
(b)
(c)
(d)
(e)
(f)
(g) Fig. 6 Dynamic response of DSRF PLL under unbalanced grid conditions (a) grid voltage waveforms (b) d and q axis positive sequence component of grid voltage (c) d and q axis negative sequence component of grid voltage (d) detected angular frequency of positive sequence component (e) detected angular frequency of negative sequence component (f) detected phase angle of positive sequence component (g) detected phase angle of negative sequence component. Fig 6(a) shows a 3-phase signal which is balanced up to time t=0.4 sec and then voltage amplitude of 2 of the phases reduces to 0.5 from their initial value of 1.5. With this kind of input the dynamic responses are observed. The positive and negative sequence components are separately observed in case of DSRF PLL. In Fig 6(b) the d axis voltage of positive sequence component is almost constant both during balanced and unbalanced period and negligible sinusoidal variations are observed during the transient period (from t=0.4 to 0.42 sec). The q axis voltage of the positive sequence component maintains mostly a constant value both in balanced and unbalanced conditions. The transients are observed when there is sudden change in input voltage (at t=0.4 sec). The transient vanishes to give a nearly constant value (nearly at zero) for q axis voltage of positive sequence component. As shown in Fig 6(c) the d axis voltage of negative sequence component is also almost constant having negligible variations. The q axis voltage of the negative sequence component maintains mostly a constant value both in balanced and unbalanced conditions. The transients are observed when there is sudden change in input voltage (at t=0.4 sec). The transient vanishes to give a nearly constant value (nearly at zero) for q axis voltage of negative sequence component. In Fig 6(d) the angular frequencies of positive and negative sequence components are both similar to their respective q axis voltages and hence a nearly constant angular frequency is observed for positive and negative sequence components. Fig 6(e) shows that the angular frequencies of positive and negative sequence components are both similar to their respective q axis voltages and hence a nearly constant angular frequency is observed for positive and negative sequence components.
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In Fig 6(f) for the constant angular frequencies we observe perfectly triangular phase angle detection for positive sequence. The detected phase angle varies linearly every cycle from 0 to 2π for positive sequence. In Fig 6(g) for the constant angular frequencies we observe perfectly triangular phase angle detection for negative sequence. The detected phase angle varies linearly every cycle from 0 to -2π for negative sequence.
C. Response of DSRF PLL Under Line to Ground fault
The results obtained from simulation for DSRF PLL underline to ground fault are shown in Fig. 7. The PI tuning used for these results are Kp =67.5 and Ki =100.
(a)
(b)
(c)
(d)
(e)
(f)
(g) Fig. 7 Simulation results obtained for DSRF PLL under line to ground fault (a) grid voltage waveforms (b) d axis and q axis positive sequence component of grid voltage (c) d axis and q axis negative sequence component of grid voltage (d) detected angular frequency of positive sequence component (e) detected angular frequency of negative sequence component (f) detected phase angle of positive sequence component (g) detected phase angle of negative sequence component. Fig. 7(a) shows the input to the system when line to ground fault occurs. The system was initially in balanced condition (having amplitude 1.5V). Line to ground fault occurs at time, t = 0.4sec.At this instant the phase voltage of 2 of the phases increases and remains at an amplitude of 2.4V. The system regains its balanced state at time, t = 0.5 sec. The d axis voltage of positive sequence component shown in Fig. 7(b) is constant at the amplitude of the signals during balanced input. During line to ground fault the d axis voltage reduces and some oscillations with very small amplitude are observed. The d axis voltage for negative sequence component (Fig.7(c)) also maintains its constant value other than very small transients that occur at time t = 0.4 sec and 0.5 sec. The q axis voltages for positive sequence (Fig. 7(b)) and negative sequence (Fig. 7(c)) maintains their near zero value at all Instants, with some oscillations at the instants when switching of voltages occur. The angular frequencies of positive sequence and negative sequence components maintain their constant value at 100 π and -100 π (Fig. 7(d) and Fig. 7(e) respectively).Therefore the detected phase angle is perfectly triangular for both positive (Fig. 7(f)) and negative sequence (Fig. 7(g)).
D. Response of DSRF PLL Under Voltage Sag
The simulation results obtained for DSRF PLL under Voltage sag are shown in Fig. 8.The PI tuning used for these results are K p = 67.5 and K I =100.
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(a)
(b)
(c)
(d)
(e)
(f)
(g) Fig. 8 Simulation results obtained for DSRF PLL under voltage sag (a) grid voltage waveforms (b) d axis and q axis positive sequence component of grid voltage (c) d axis and q axis negative sequence component of grid voltage (d) detected angular frequency of positive Sequence component (e) detected angular frequency of negative sequence component (f) detected phase angle of positive sequence component (g) detected phase angle of negative sequence component As shown in Fig. 8(a), voltage sag occurs at time t = 0.3 sec when all the three phases voltages reduces to 0.45V from their initial voltage of 0.5V. The 3 phases regain their original value of 0.5V at time t = 0.4 sec. This kind of sudden reduction is voltage for small period (2 and half cycles in this case) is known as voltage sag.Fig.8 (b) illustrates the d axis voltage of positive sequence component, which is constant at the amplitude of the input signal. In the duration when voltage sag occurs, the d axis voltage remains constant but its value changes to the new amplitude. Similarly as shown in Fig. 8(c) the d axis voltage of negative sequence component also maintains its constant zero value. The q axis voltage of positive sequence component remains constant at a value very close to zero and some slight transients are observed at the time of switching (Fig. 8 (b). The same holds good for q axis voltage of negative sequence component which remains constant at zero in both the periods (Fig. 8(c) ). As q axis voltages are constant the corresponding angular frequency for both positive and negative components maintains their constant value at 100 π and -100 π (Fig. 8(d) and Fig. 8(e)).The detected phase for both the sequence components is perfectly triangular because of the constant angular frequency observed.
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V. CONCLUSIONS
The paper presents the performance of Dual Synchronous Reference Frame (DSRF) PLL for phase detection under grid disturbances. The grid disturbances include, voltage unbalance, line to ground fault and voltage sag. From the above discussions, one can observe that, the studied DSRF PLL can accurately detect the phase irrespective of the grid conditions. Moreover, the DSRF PLL can also decouple the positive and negative sequence components of grid voltages in order to ensure sinusoidal current injection into the Grid. Further, the obtained results clearly show that the DSRF PLL gives better response to track the positive sequence component over conventional SRF PLL which fails to track the phase angle whenever there is an unbalance in the grid. On the other hand DSRF PLL properly handles the abnormalities and the phase angle is perfectly detected in each case. The improvement in this study will be enhanced by implementing the DSRF PLL in digital platform using FPGA in the future work.
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