Aditya Gujja is seeking a full-time opportunity in digital circuit design research and development. He has an MS in Electrical Engineering from Arizona State University and a BE in Electronics and Communications from Osmania University. His work experience includes being a teaching assistant for Advanced VLSI Design at ASU and a research assistant to Dr. L. T. Clark from summer 2014 to present. His research focuses on radiation hardened pulse clocked latch design and static and dynamic register file design.

1. ADITYA GUJJA
www.linkedin.com/in/adityagujja
♦1255 E University Dr, A304, Tempe, AZ 85281. ♦631-882-0665 ♦Aditya.Gujja@asu.edu
OBJECTIVE
Seeking Full Time opportunity in digital circuit design research and development to gain knowledge and apply my skills.
EDUCATION
MS (Electrical Engineering) - Arizona State University, exp. Oct 2015 GPA: 3.4/4.0
BE (Electronics & Communications) - Osmania University, May 2013 GPA: 3.4/4.0
WORK EXPERIENCE
• Teaching Assistant (TA) for Advanced VLSI Design at ASU Fall 2014
• Research Assistant (RA) to Prof Dr. L. T. Clark, summer 2014 - present
TECHNICAL SKILLS
EDA Tools : Cadence Spectre, Virtuoso, SoC Encounter, ELC, Hspice, ModelSim, Ultrasim, Formality,
AbstractGen, Nanotime, Primetime, RTL compiler.
Programming Languages : Perl, C, Embedded C, Assembly Language, Verilog, System Verilog.
Operating Systems : Windows, Linux, Mac-OS.
RESEARCH PUBLICATIONS
• A. Gujja, S. Chellappa, C. Ramamurthy and L. T. Clark, “ Redundant Skewed Clocking of Pulse-clocked Latches for Low
Power Soft Error Mitigation ” (Accepted to RADECS 2015).
• A. Gujja, S. Chellappa, C. Ramamurthy, L.T. Clark, “Muller C-element as Majority gate for self-correcting triple mode
redundant logic” (submitted to Electronics Letters).
• V. Vashishtha, A. Gujja, L. T. Clark, “ Delay and Power Tradeoffs for Static and Dynamic Register Files” (ISCAS 2015).
• V. Vashishtha, L. T. Clark, S. Chellappa, A. R. Gogulamudi, A. Gujja, and Chad Farnsworth, “A Soft-Error Hardened Process
Portable Embedded Microprocessor” (Accepted to CICC 2015).
INVENTION DISCLOSURES
• A. Gujja, S. Chellappa, V. Vashishtha, L.T. Clark, “Muller C-element as Majority gate for self-correcting triple mode
redundant logic”
RESEARCH WORK June 2014 - present
• Masters Dissertation: Temporal Clocks based Radiation hardened Pulse FF design
o Designed and implemented a globally redundant temporal pulse clocked latch based AES design in TSMC90.
o Optimized for performance at 200 MHz and achieved 20% power and 5% area savings over previous designs.
o Test chip was verified hard to radiation induced soft errors by broad beam proton testing at UC Davis.
o Embedded single/triple redundant modes and hold fixings to operate in different modes.
• Static and Dynamic Register File Design
o Designed and implemented 16x128 Dynamic and Static Register files to analyze functional performance.
o Static RF design was fabricated in TSMC90 and performance ensured through post silicon validation.
o Modified Static RF was used to implement a write-through cache for a radiation hardened microprocessor.
• XOR Clock Frequency Multiplier Circuit for the Radiation hardened microprocessor, working on silicon.
o Optimized the design to get equal raise and fall times, Jitter of about 10ps.
• Proposed and verified a C-element based Majority gate for self-correcting TMR FF designs.
o Supports independent domain testing, multiple parallel or single thread operation, saves power (10%) and area (20%).
• Designed the 7nm Finfet PDK in association with ARM holdings.
o Studied the characteristics of Finfet’s, Lithography techniques and process variations to the design rules.
o Built SRAM and standard cells to verify DRC and LVS, extracted netlist to verify their functionality.
o Mentor graphics course for DRC rules.
ACADEMIC PROJECTS
• 8kB 4-way set-associative Cache implementation using 16x128 Dynamic RF
• ASIC Design of Single Cycle 32 bit MIPS Processor in Synopsys 32nm PDK
o Complete design from RTL synthesis to GDSII, including floor planning, Placement, clock tree synthesis, Optimizing the
design and Primetime timing analysis.
• 32bit Non-pipelined Single cycle MIPS Processor using Verilog and system Verilog verification.
• Designed an Asynchronous FIFO containing memory and comparator modules using Verilog.
o Tested to FIFO full and empty conditions with write clock at 100 MHz and read at 10 MHz frequencies.
• Designed a Low Dropout (LDO) Regulator to a stable 2.25V (+/- 5% ripple) with varying loads from 1 mA to 50 mA current.
COURSE WORK: Sub 10nm PDK design, Advanced VLSI, VLSI Design, Computer Architecture, Verilog and System Verilog,
Digital Systems and Circuits, Semiconductor Device Theory, Nano-scale Fab Char, Analog Integrated Circuit.