1. JEYAKUMAR R
Address: 5/485A Krishna Nagar Krishnankovil
Srivilliputhur Tamilnadu -626190
LinkedIn: linkedin.com/in/jeyakumar-r-0bb17934
Phone: 9688571755
Email: r.jeyakumar23@gmail.com
Snapshot
Self-motivated VLSI engineer with 2 years of Industrial experience in Automotive ECU Verification and Validation. Currently
pursuing Masters in Vellore Institute of Technology specializing in VLSI Design.
Education
M.Tech VLSI
DESIGN Vellore Institute of Technology 2015-2017
CGPA- 9.44
Rank: 2/105
B.E (ECE) Madras Institute of Technology
Anna University.
2009-2013
CGPA-8.67
First Class with Distinction
H.S.C Chinmaya Vidyalaya Rajapalayam March 2009
96.6%
(100% in maths)
H.S.L.C Chinmaya Vidyalaya Rajapalayam March 2007 93%
Industrial Experience
Delphi Automotive Systems Aug 2013 – July 2015
JCB-SEF (SMALL ELECTRONICS FAMILY)
Objective: To support customer requirements and deliver high quality software for the Medium duty vehicles
Responsibilities:
 Implemented J1939 protocol messages.
 Performed Unit Testing and Bench validation for each release
 Proposed new algorithm for the Integration Review Execution which reduces the space in the server
 S-function testing for the Auto code models
CAM-CRANK PROJECT
Objective: To code and flash the pattern exactly into the speed box for the specific project.
Responsibilities:
 Implemented a Tool which can create a Crank and CAM
 Static and Dynamic (functionality) tests using Polyspace and Rational Test Real Time.
 Software Integration Review tasks which checks if integration of files meant for each software release baselines are
done correctly.
Technical Skills
 Programming Languages: Verilog, C, Perl, Matlab and TCL
 VLSI Designing Tools: Cadence Virtuoso, Synopsys- Design Compiler, IC-Compiler, Modelsim, Quartus 
 Embedded Tools: Polyspace, RTRT, Clear case, VISU and DDS Flasher.
Coursework
Graduate Level: CAD for VLSI, Semiconductor Physics, FPGA, ASIC Design, Analog IC Design, Digital IC Design, Testing and
Testability, Low Power VLSI, SOC and Scripting Languages.
Undergraduate Level: Digital Electronics, Analog circuits, Digital and Analog Communications, Networks.

2. Graduate Academic Projects:
STUCK AT FAULT ANALYSIS IN SCAN CHAIN ARCHITECTURE
 Implemented a new hardware architecture to detect the stuck at faults in scan chains. 
 Achieved a reduction of one XOR gate for every 8 flip flops. 
FPGA IMPLEMENTATION OF VIDEO SENSOR BASED HUMAN ACTIVITY RECOGNITION SYSTEM
 The aim of this project is to detect the abnormal activities of elderly people staying alone at home. The health problem
and their regular activities of day to day life are taken as references and then comparing the activities for detecting the
abnormal one.
REDUCING THE ON SWITCH RESISTANCE IN DICKSON CHARGE PUMP
 On switch resistance of the MOSFET cannot be ignored in Dickson Charge Pump when it transfers the charge from one
stage to another. Hence a method using Transmission gates and it has successfully reduced the resistance.
MATLAB CODE TO DETERMINE ZERO CLOCK SKEW
 To find the source of the clock for the given clock sinks using the exact zero skew
algorithm.
Undergraduate Academic Projects:
VLSI IMPLEMENTATION OF FULL BRIDGE SINUSOIDAL PULSE WIDTH MODULATION:
 Selectively eliminate higher order harmonics in the output of the inverter by using PWM technique.
Tools: OrCAD PSPICE and ALTERA QUARTUS
ANDROID APPLICATION FOR RETINAL DIAGONOSIS:
 Using Android SDK and Eclipse IDE created an android application that will detect retina and tell user about the extent
of the disease. And also created small applications like silent phone, automatic counter etc.
AUTOMATED PUBLIC DISTRIBUTION SYSTEM:
 Barcode reader will read the barcode imprinted on the ration card and as soon as the user gives the command the
products to be given to the customer will be readily issued by the vending machine.
RAILWAY RESERVATION SOFTWARE IN C++:
 Developed a program which automatically allots seat and fare for list of passengers given as input. We can also check
PNR number using it.
LINE FOLLOWER ROBOT:
 Used IR sensors and logic gates developed a robot that senses the black line and traced the path
Publications – Indexed in IEEE Xplore
FPGA Implementation of Edge Detection using Canny Algorithm IC-GET-2015
Awards and Achievements
2016 MERIT Award Merit Scholarship was given for securing 2nd rank out of 105 students. VIT
2015 SPOT Award
Received an appreciation for finding a bug in 3-Driving Mode for TATA Kite
vehicle before delivering to the customer . DELPHI
2012 Bronze Medal Zonal Level Chess Tournament Tamil Nadu