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# Session one

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### Session one

1. 1. http://www.bized.co.uk Session 1Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
2. 2. http://www.bized.co.ukContents -Introduction to VHDL - ASIC & FPGA Design flow 1 -How to read and write VHDL code - Library and package - Entity - Basic data types - Architecture - Demo no. 1 Using Xilinx and Modelsim tools 2 Copyright 2006 – Biz/ed
3. 3. Session 1 http://www.bized.co.uk Introduction to VHDL 3 Copyright 2006 – Biz/ed
4. 4. Session 1 http://www.bized.co.ukDesigning with Boolean EquationsBoolean equations are impractical for large design containing hundreds of flip flopsbecause it could result in a huge number of logical equations. X= A.B 4 Copyright 2006 – Biz/ed
5. 5. Session 1 http://www.bized.co.ukSchematic based design-Schematic based design expanded thecapabilities of Boolean equations.-The major drawback of traditional designmethods is the manual translation of designdescription into a set of logical equations.-This step can be entirely eliminated withhardware description languages (HDLs). 5 Copyright 2006 – Biz/ed
6. 6. Session 1 http://www.bized.co.ukHardware Description Language [HDL]Question:How do we know that we have not made a mistake whenwe manually draw a schematic and connect componentsto implement a function?Answer:By describing the design in a high-level [such as (c,basic…)] language, we can simulate our design beforewe manufacture it. This allows us to catch design errors,i.e., that the design does not work as we thought it would.• Simulation guarantees that the design behaves as itshould.HDL is short for Hardware Description Language 6 Copyright 2006 – Biz/ed
7. 7. Session 1 http://www.bized.co.ukWhat is VHDL ?-Very high speed integrated circuit Hardware Description Language-Early 1980s : It was developed by the U.S. Department of Defense-1987 : IEEE Std 1076 - 87-1993 : Added some new features and became IEEE Std 1076 – 93-1999 : An extension to the language called VHDL – AMS Analog Mixed Signal extension-2008: IEEE Std 1076 – 2008 (New features) 7 Copyright 2006 – Biz/ed
8. 8. Session 1 http://www.bized.co.uk Design Flow 8 Copyright 2006 – Biz/ed
9. 9. Session 1 http://www.bized.co.uk SpecificationsASIC and FPGA Design Flow System Level Design Function RTL Description Verification Gate Level Synthesis Simulation Place &Route Fabrication Configuration ASIC FPGA 9 Copyright 2006 – Biz/ed
10. 10. Session 1 http://www.bized.co.ukASIC and FPGA Design FlowSpecification is an set of requirements before designing the systemRTL Description Register-Transfer Level (RTL)Function Verification Does this proposed design do what is intended?Synthesis Convert RTL description into a H/W.Placement Deciding where to place all electronic components.Routing Wiring the placed componentsThis last two steps depend on the rules and limitations of the manufacturing process. 10 Copyright 2006 – Biz/ed
11. 11. Session 1 http://www.bized.co.ukVHDL Language ScopeThere is two types of toolsthat deal with VHDL-Simulationto test the logic design using simulation models ―All Language syntax used‘‘-Synthesisto convert codes to hardware―pare of Language syntax used‖ 11 Copyright 2006 – Biz/ed
12. 12. Session 1 http://www.bized.co.uk How to read VHDL code 12 Copyright 2006 – Biz/ed
13. 13. Session 1 http://www.bized.co.ukLibrary and Package The first lines that you will find at the top of any project Library and Packages define special types used in the code; 13 Copyright 2006 – Biz/ed
14. 14. Session 1 http://www.bized.co.ukDesign UnitsThere are two types of design units in VHDL–Primary Not dependent upon other design units Entity (Interface) ? How the system will communicate with the outside world–Secondary Depends on primary design unit Architecture (Function ) –What the system should do ?-No secondary can exist as stand-alone—without the primary-Whenever the primary design unit changes, the secondary design must bereanalyzed 14 Copyright 2006 – Biz/ed
15. 15. Session 1 http://www.bized.co.ukEntityDefine ports (inputs and outputs) of the module i.e the interface of the blockEntity declaration entity <entity_name> is port ( <port_name> : <mode> <type>; <port_name> : <mode> <type>; … <port_name> : <mode> <type> ); End <entity_name> ; 15 Copyright 2006 – Biz/ed
16. 16. Session 1 http://www.bized.co.ukEntity- <entity_name> Define the port name - VHDL is case Insensitive ----- Important Note - Don‘t start the port name or entity name of the port with Underscore _ or number- <mode> Define the port direction IN : Only read from it OUT : Only write on it INOUT : read from or write on it (controlled by another signal)- <type> Define the port data type --------------------------------------------------------------------------------------------- Last port has no semicolon ;- Line Comments started by - -- Comma , can separate ports with the same type and mode - A,b : in bit ; 16 Copyright 2006 – Biz/ed
17. 17. Session 1 http://www.bized.co.ukQuestion System A is composed of system B,C and D. Determine the entity of system A? 17 Copyright 2006 – Biz/ed
18. 18. Session 1 http://www.bized.co.uk• Entity of 2-input AND Gate A C B AND Gate Example 1 18 Copyright 2006 – Biz/ed
19. 19. Session 1 http://www.bized.co.ukEntity of 2-input AND Gate A C B AND_GATE ENTITY AND_GATE IS port ( a : in BIT; b : in BIT; C : out BIT ); -- inputs and outputs of the entity END ENTITY AND_GATE ; Important Note to make a comment in VHDL you can put (--) before any line you need it to be a comment. 19 Copyright 2006 – Biz/ed
20. 20. Session 1 http://www.bized.co.ukBasic data types VHDL is strongly typed BIT STD_LOGIC 0 1 0 1 H L UDefault X W Z - Default value valueBIT_VECTOR : STD_LOGIC_VECTOR :1D-array each element of the BIT type 1D-array each element of the STD_LOGIC typeExample: Example:a : in BIT; a : in STD_LOGIC;b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0);c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3); 20 Copyright 2006 – Biz/ed
21. 21. Session 1 http://www.bized.co.ukBasic data types X Z 0 1 UUnknown High Strong Strong Unitialized Impedance Zero One Default value W - H L Weak Don‘t Weak Weak Unknown care One Zero To define std_logic data type LIBRARY ieee; USE ieee.std_logic_1164 .all; 21 Copyright 2006 – Biz/ed
22. 22. Session 1 http://www.bized.co.uk• Entity of 2-input AND Gate using STD_LOGIC type A C B AND Gate Example 2 22 Copyright 2006 – Biz/ed
23. 23. Session 1 http://www.bized.co.ukEntity of 2-input AND Gate using STD_LOGIC type LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY AND_GATE IS port ( a : in STD_LOGIC; b : in STD_LOGIC; C : out STD_LOGIC ); END ENTITY AND_GATE ; A C B AND_GATE 23 Copyright 2006 – Biz/ed
24. 24. Session 1 http://www.bized.co.ukArchitectureDescribe the operation (relations between inputs and outputs) of the module i.e the Body of the blockArchitecture declaration architecture <arch_name> of <entity_name> is -- architecture declarations begin -- architecture body end <arch_name> ; 24 Copyright 2006 – Biz/ed
25. 25. Session 1 http://www.bized.co.ukArchitectureNon-Blocking assignment <= c <= a and b ;Note -the LHS  Outputs only as we write on it -the RHS  Inputs only as we read from it and make operations on itTo assign a value in std_logic or bit type c <= „0‟; or c <= „1‟;To assign a value in std_logic_vector or bit_vector type c <= “10……1001”; 25 Copyright 2006 – Biz/ed
26. 26. Session 1 http://www.bized.co.uk• 2-input AND Gate A C B AND Gate Example 3 26 Copyright 2006 – Biz/ed
27. 27. Session 1 http://www.bized.co.uk2-input AND Gate LIBRARY ieee; A C USE ieee.std_logic_1164.all; B AND_GATE ENTITY AND_GATE IS port ( a : in std_logic; b : in std_logic; C : out std_logic ); -- inputs and outputs of the entity END ENTITY AND_GATE ; ARCHITECTURE behave OF AND_GATE IS BEGIN c <= a and b; --non blocking assignment END ARCHITECTURE behave; 27 Copyright 2006 – Biz/ed
28. 28. Session 1 http://www.bized.co.uk• N-bits AND Gate A C B AND Gate Example 4 28 Copyright 2006 – Biz/ed
29. 29. Session 1 http://www.bized.co.ukLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; Libraries & Packages headersENTITY and_gate IS port ( A : in std_logic_vector (3 downto 0); B : in std_logic_vector (3 downto 0); Interface definition C : out std_logic_vector (3 downto 0) (input/output ports) );END ENTITY and_gate ;ARCHITECTURE behave OF and_gate ISBEGIN c<= a and b; Functional/behavioralEND ARCHITECTURE behave; ImplementationImportant Note If we need to use a specific bit in vector C,A or B If we want to put ‗1‘ onsode 2nd bit in vector C then we say C(1) ex : c(2) <= ‗1‘; 29 Copyright 2006 – Biz/ed
30. 30. Session 1 http://www.bized.co.ukUsing Xilinx and Modelsim tools 30 Copyright 2006 – Biz/ed
31. 31. Session 1 http://www.bized.co.ukWriting code that describe the Entity and Architecture of 2-XOR Gate of 2 bit width,Simulating it on Modelsim and using Xilinx ISE synthesis tool. 2 A 2 XOR C 2 B 31 Copyright 2006 – Biz/ed
32. 32. Session 1 http://www.bized.co.ukAssignment Session-1Read Session-1 Notes carefully to be ready for the next session‘s QUIZ 32 Copyright 2006 – Biz/ed
33. 33. Session 1 http://www.bized.co.ukDownload Session 1 material Introduction to the course.pdf Session 1.pdf Demo 1.txtAsk for the material through mail start.courses@gmail.comFacebook group start.group@groups.facebook.com 33 Copyright 2006 – Biz/ed
34. 34. Session 1 http://www.bized.co.ukQuestions Session-1 34 Copyright 2006 – Biz/ed
35. 35. Session 1 http://www.bized.co.ukTake Your Notes Print the slides and take your notes here--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 35 Copyright 2006 – Biz/ed
36. 36. Session 1 http://www.bized.co.ukSee You Next Session 36 Copyright 2006 – Biz/ed