The document discusses techniques to reduce structural bias in technology mapping. It proposes using supergates, which combine multiple library gates, to allow matches that intermediate points not present in the original circuit. It also describes performing lossless synthesis to merge equivalent networks and add choice nodes. Experimental results show the combined approach of supergates and lossless synthesis improves delay and area over the baseline.

1. Reducing Structural Bias in Technology Mapping Satrajit Chatterjee, Alan Mishchenko and Robert Brayton U. C. Berkeley Xinning Wang and Timothy Kam Intel Corp. ICCAD / 8 Nov 2005

3. Technology Mapping Input: A set of gates and a Boolean network Output: A netlist of gates imple- menting the Boolean network a b c d f a b c d f The library The subject graph The mapped netlist Technology Mapping 1 0

4. Structural Bias The mapped netlist very closely resembles the subject graph a b c d f p a b c d f p Every input of every gate in the mapped netlist must be present in the subject graph .. .. otherwise technology mapping will not find the match

5. The Problem of Structural Bias A better match may not be found a b c d f p a b c d f p 1 0 a b c d f q Since the point q is not present in the subject graph, the match on the extreme right will not be found This match is not found

7. Supergates Idea: Combine multiple library gates into a single gate for mapping Examples of some supergates generated from the library The library Supergate Generation 1 0 1 0

8. Supergates Help Since the whole supergate is matched at a time, the presence of intermediate points is not required in the subject graph a b c d f r 1 0 a b c d f q r Observe that the point q is not required in the subject graph since it is now an internal point of the supergate, so the match is found

12. Traditional Synthesis Technology- independent synthesis sweep eliminate resub simplify fx resub sweep eliminate sweep full simplify Boolean Network Technology Mapping Mapped Netlist Only the network at the end of technology independent synthesis is used for mapping No guarantee of optimality since each synthesis step is heuristic. But structural bias means the mapped netlist depends heavily on the final network.

13. Lossless Synthesis sweep eliminate resub simplify fx resub sweep eliminate sweep full simplify Boolean Network Technology Mapping Mapped Netlist Technology mapping is not any harder with choices (Lehman-Watanabe ‘95) Technology- independent synthesis Idea: Merge intermediate networks into a single network with choices which is used for mapping Choice operator

14. Lossless Synthesis sweep eliminate resub simplify fx resub sweep eliminate sweep full simplify Boolean Network Technology Mapping Mapped Netlist speed up reduce depth Script optimizes area Script optimizes delay Can combine the results of different technology independent optimization scripts

15. Mapping with Choices sweep eliminate resub simplify fx resub sweep eliminate sweep full simplify Boolean Network Technology Mapping Mapped Netlist Question 1: How to implement an efficient choice operator? Question 2: How to map quickly with choices?

18. Detecting Choices a b c d x y Step 3: Merge equivalent nodes with choice edges x now represents a class of nodes that are functionally equivalent up to complementation a b c d x y a b c d x y

21. k -feasible Cuts a b c p q r (Rough definitions) A cut of a node n is a set of nodes in transitive fan-in such that assigning values to those nodes fixes the value of n. A k-feasible cut means the size of the cut must be k or less. The set {p, b, c} is a 3-feasible cut of node r . (It is also a 5-feasible cut.) k -feasible cuts are important in Boolean matching, because the logic between a node and the nodes in its cut can be replaced by a suitable gate from the library.

22. k -feasible Cut Computation a b c p q { {p}, {a, b} } { {q}, {b, c} } { {a} } { {b} } { {c} } r { {r}, {p, q}, {p, b, c}, {a, b, q}, {a, b, c} } The set of cuts of a node is a ‘cross product’ of the sets of cuts of its children Any cut that is of size greater than k is discarded Computation is done bottom-up (Pan ’98, Cong ’99)

23. Cut Computation with Choices Cuts are now computed for equivalence classes of nodes Cuts ( x ) = Cuts ( x 1 )  Cuts( x 2 ) = { {x 1 }, {p, r}, {p, b, c}, {a, c, r}, {a, b, c}, {x 2 }, {q, c} } a b c d x y x 1 x 2 p q r { {x 1 }, {p, r}, {p, b, c}, {a, c, r}, {a, b, c} } { {x 2 }, {q, c}, {a, b, c} }

26. Experimental Comparison Baseline is fast: 10K gates in 3 sec. Choice detection run-time is 3x baseline. Comparison of various techniques to reduce structural bias (Current version / newer than paper) Comparison with algebraic choices (a la Lehman-Watanabe) Delay improvement over the mode 28.91 1.13 0.68 B-L-S 7.00 1.11 0.75 B-S (Supergates) 3.79 1.03 0.79 B-L (Lossless) 1.00 1.00 1.00 B (Baseline) Run-time Area Delay Mode 4% B-L 9% B 2% B-L-S 4% B-S

27. Experimental Comparison Comparison with other mappers on industrial examples -209.11 205.00 -189.73 323.00 -225.11 239.00 ex12 0.81 0.94 0.85 1.20 1.00 1.00 Average -60.89 72.00 -60.16 85.00 -74.80 91.00 ex11 -44.55 105.00 -44.65 92.00 -48.11 102.00 ex10 -111.62 98.00 -133.96 154.00 -146.78 96.00 ex9 -53.96 47.00 -53.42 47.00 -56.45 41.00 ex8 -53.96 47.00 -53.42 47.00 -56.45 41.00 ex7 -93.16 88.00 -101.37 103.00 -123.02 103.00 ex6 -129.81 102.00 -132.92 156.00 -162.49 118.00 ex5 -123.45 171.00 -131.92 208.00 -177.89 177.00 ex4 -72.71 54.00 -78.03 61.00 -92.44 53.00 ex3 -75.03 55.00 -76.06 59.00 -92.64 51.00 ex2 -89.74 40.00 -115.18 49.00 -124.90 42.00 ex1 wns area wns area wns area B-S-L GraphMap DAG Mapper Design