This document describes the design of a parallel self-timed adder called PASTA that uses a recursive approach. PASTA performs multi-bit binary addition without needing any carry chain propagation. It works by first accepting two input operands and performing half additions for each bit, then iteratively using the previous sums and carries to perform additional half additions until all carries settle to zero. The architecture of PASTA uses multiplexers to select between the actual operands and feedback paths from previous half additions. Simulation results show its advantages over traditional approaches in reducing delay and improving efficiency.
Extrapolation of Stage Discharge Rating CurveBiswajit Dey
An accurate stage–discharge relationship is necessary for design to evaluate the interrelationships of flow characteristics (depth and discharge)
The stage-discharge relationship also enables you to evaluate a range of conditions as opposed to a preselected design flow rate.
Continuous measurement of discharge in a river is a very costly, time-consuming, and impractical exercise, especially during floods.
Usually, to overcome limitations to continuous discharge measurement, observed stage data is converted into river discharge using a stage-discharge relationship, commonly known as the rating curve.
Rating curve is considered as an epitome of all the channel characteristics
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...Hardik Parikh, E.I.T.
The research has shown that SVC has been proved successful to prevent negative sequence current more over it also has capabilities for Power factor correction.
• Negative-sequence current causes some problems in generator systems. Though every generator is capable of withstanding a certain level of negative-sequence current, excess and/or persistent amounts of negative sequence current may cause rotor overheating and serious damage.
• Since its frequency quite matches the natural mechanical frequency of turbine blades and the zero sequence current is blocked by delta connected step-up transformer, the negative sequence current becomes the only reason for the super synchronous resonance of a generator due to an unbalanced system, especially in an isolated power system.
• SVC has the potential to overcome some adverse effects of the negative sequence current to the turbine generator systems
The presentation covers synchronous sequential circuit elements; latch and Flip flops, SR Flip flop, JK Flip flop, T flip flop, D Flip flop, race around condition, Edge triggered flip flop
Implementation of Linear Controller for a DC-DC Forward Converterijceronline
This paper discusses the controller implementation of a DC to DC Forward converter. The open loop response is obtained initially. Then the closed loop control is given in real time for the Forward converter. The MATLAB interfacing is done with the help of data acquisition card. The conventional PI controller is used for the closed loop control and the results are analyzed under MATLAB/SIMULINK environment
Extrapolation of Stage Discharge Rating CurveBiswajit Dey
An accurate stage–discharge relationship is necessary for design to evaluate the interrelationships of flow characteristics (depth and discharge)
The stage-discharge relationship also enables you to evaluate a range of conditions as opposed to a preselected design flow rate.
Continuous measurement of discharge in a river is a very costly, time-consuming, and impractical exercise, especially during floods.
Usually, to overcome limitations to continuous discharge measurement, observed stage data is converted into river discharge using a stage-discharge relationship, commonly known as the rating curve.
Rating curve is considered as an epitome of all the channel characteristics
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...Hardik Parikh, E.I.T.
The research has shown that SVC has been proved successful to prevent negative sequence current more over it also has capabilities for Power factor correction.
• Negative-sequence current causes some problems in generator systems. Though every generator is capable of withstanding a certain level of negative-sequence current, excess and/or persistent amounts of negative sequence current may cause rotor overheating and serious damage.
• Since its frequency quite matches the natural mechanical frequency of turbine blades and the zero sequence current is blocked by delta connected step-up transformer, the negative sequence current becomes the only reason for the super synchronous resonance of a generator due to an unbalanced system, especially in an isolated power system.
• SVC has the potential to overcome some adverse effects of the negative sequence current to the turbine generator systems
The presentation covers synchronous sequential circuit elements; latch and Flip flops, SR Flip flop, JK Flip flop, T flip flop, D Flip flop, race around condition, Edge triggered flip flop
Implementation of Linear Controller for a DC-DC Forward Converterijceronline
This paper discusses the controller implementation of a DC to DC Forward converter. The open loop response is obtained initially. Then the closed loop control is given in real time for the Forward converter. The MATLAB interfacing is done with the help of data acquisition card. The conventional PI controller is used for the closed loop control and the results are analyzed under MATLAB/SIMULINK environment
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
1. RECURSIVE APPROACH TO THE
DESIGN OF A PARALLEL
SELF-TIMED ADDER
By
Ms. D.Vidya (14C35A0409)
Ms. V.Pavanisujatha (13C31A04A1)
Mr.P.Chendra shekar (13C31A0471)
Under the guidance of
Ms. M. Mounika
Assistant professor
BALAJI INSTITUTE OF TECHNOLOGYAND SCIENCE
NARSAMPET, WARANGAL – 506 331
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
2. CONTENT
• INTRODUCTION
• ABSTRACT
• DESIGN OF PASTA
• ARCHITECTURE OF PASTA
• STATE DIAGRAMS FOR PASTA
• FLOW CHART
• RECURSIVE FORMULA FOR BINARY ADDITION
• SIMULATION WAVE FORM FOR RECURSIVE ADDER
• SYNTHESIS REPORT FOR RECURSIVE ADDER
• APPLICATIONS
• ADVANTAGES
• CONCLUSION
3. INTRODUCTION
• Binary addition is the single most important operation that a
processor performs.
• Asynchronous circuits do not assume any quantization of
time.
• In principle, logic flow in asynchronous circuits is controlled
by a request-acknowledgment handshaking protocol to
establish a pipeline in the absence of clocks.
4. ABSTRACT
• It is based on a recursive formulation for performing multi-bit
binary addition.
• Do not need any carry chain propagation.
• Does not have any practical limitations of high fan-outs.
• A high fan-in gate is required though but this is unavoidable
for asynchronous logic and is managed by connecting the
transistors in parallel.
5. DESIGN OF PASTA
• The adder first accepts two input operands to perform half
additions for each bit.
• Subsequently, it iterates using earlier generated carry and sums
to perform half-additions repeatedly until all carry bits are
consumed and settled at zero level.
7. Cont….
• Initially it select the actual operands during SEL = 0 and
switch to feedback/carry paths for subsequent iterations using
SEL = 1.
• The feedback path from the HAs enables the multiple
iterations to continue until the completion when all carry
signals will assume zero values.
9. Cont…..
• During the initial phase, the circuit merely works as a
combinational HA operating in fundamental mode.
• During the iterative phase (SEL = 1), the feedback path
through multiplexer block is activated.
• The carry transitions (Ci ) are allowed as many times as
needed to complete the recursion.
11. Recursive Formula for Binary Addition
• Sj
i and Cj
i+1 are the sum and carry for ith bit at the jth
iteration.
• The initial condition ( j = 0) for addition is formulated as
follows:
S0
I = ai ⊕ bi
C0
i+1= ai bi .
12. • The jth iteration for the recursive addition is formulated by
Sj
i = S j−1
i ⊕ C j−1
i , 0 ≤ i < n
C j
i+1 = S j−1
i C j−1
i , 0 ≤ i ≤ n.
• The recursion is terminated at kth iteration when the following
condition is met:
Ck
n + Ck
n−1+ ・・ ・+Ck
1= 0, 0 ≤ k ≤ n.
15. APPLICATIONS
• Digital systems designing
• Digital signal processing
• Multiplication and Accumulation
• Arithmetic and Logic Unit (ALU)
• Microprocessors
17. CONCLUSION
• The design achieves a very simple n-bit adder that is area and
interconnection-wise equivalent to the simplest adder namely
the RCA.
• Moreover, the circuit works in a parallel manner for
independent carry chains, and thus achieves logarithmic
average time performance over random input values.
• Simulation results are used to verify the advantages of the
proposed approach.