SlideShare a Scribd company logo
RECURSIVE APPROACH TO THE
DESIGN OF A PARALLEL
SELF-TIMED ADDER
By
Ms. D.Vidya (14C35A0409)
Ms. V.Pavanisujatha (13C31A04A1)
Mr.P.Chendra shekar (13C31A0471)
Under the guidance of
Ms. M. Mounika
Assistant professor
BALAJI INSTITUTE OF TECHNOLOGYAND SCIENCE
NARSAMPET, WARANGAL – 506 331
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CONTENT
• INTRODUCTION
• ABSTRACT
• DESIGN OF PASTA
• ARCHITECTURE OF PASTA
• STATE DIAGRAMS FOR PASTA
• FLOW CHART
• RECURSIVE FORMULA FOR BINARY ADDITION
• SIMULATION WAVE FORM FOR RECURSIVE ADDER
• SYNTHESIS REPORT FOR RECURSIVE ADDER
• APPLICATIONS
• ADVANTAGES
• CONCLUSION
INTRODUCTION
• Binary addition is the single most important operation that a
processor performs.
• Asynchronous circuits do not assume any quantization of
time.
• In principle, logic flow in asynchronous circuits is controlled
by a request-acknowledgment handshaking protocol to
establish a pipeline in the absence of clocks.
ABSTRACT
• It is based on a recursive formulation for performing multi-bit
binary addition.
• Do not need any carry chain propagation.
• Does not have any practical limitations of high fan-outs.
• A high fan-in gate is required though but this is unavoidable
for asynchronous logic and is managed by connecting the
transistors in parallel.
DESIGN OF PASTA
• The adder first accepts two input operands to perform half
additions for each bit.
• Subsequently, it iterates using earlier generated carry and sums
to perform half-additions repeatedly until all carry bits are
consumed and settled at zero level.
ARCHITECTURE OF PASTA
Cont….
• Initially it select the actual operands during SEL = 0 and
switch to feedback/carry paths for subsequent iterations using
SEL = 1.
• The feedback path from the HAs enables the multiple
iterations to continue until the completion when all carry
signals will assume zero values.
State Diagram for PASTA
Cont…..
• During the initial phase, the circuit merely works as a
combinational HA operating in fundamental mode.
• During the iterative phase (SEL = 1), the feedback path
through multiplexer block is activated.
• The carry transitions (Ci ) are allowed as many times as
needed to complete the recursion.
FLOW CHART
Recursive Formula for Binary Addition
• Sj
i and Cj
i+1 are the sum and carry for ith bit at the jth
iteration.
• The initial condition ( j = 0) for addition is formulated as
follows:
S0
I = ai ⊕ bi
C0
i+1= ai bi .
• The jth iteration for the recursive addition is formulated by
Sj
i = S j−1
i ⊕ C j−1
i , 0 ≤ i < n
C j
i+1 = S j−1
i C j−1
i , 0 ≤ i ≤ n.
• The recursion is terminated at kth iteration when the following
condition is met:
Ck
n + Ck
n−1+ ・・ ・+Ck
1= 0, 0 ≤ k ≤ n.
SIMULATION WAVE FORM FOR
RECURSIVE ADDER
SYNTHESIS REPORT FOR RECURSIVE
ADDER
APPLICATIONS
• Digital systems designing
• Digital signal processing
• Multiplication and Accumulation
• Arithmetic and Logic Unit (ALU)
• Microprocessors
ADVANTAGES
• Delay will be reduced.
• Area Efficient adders.
CONCLUSION
• The design achieves a very simple n-bit adder that is area and
interconnection-wise equivalent to the simplest adder namely
the RCA.
• Moreover, the circuit works in a parallel manner for
independent carry chains, and thus achieves logarithmic
average time performance over random input values.
• Simulation results are used to verify the advantages of the
proposed approach.
Any Queries??????
presentation on pasta

More Related Content

Similar to presentation on pasta

Extrapolation of Stage Discharge Rating Curve
Extrapolation of Stage Discharge Rating CurveExtrapolation of Stage Discharge Rating Curve
Extrapolation of Stage Discharge Rating Curve
Biswajit Dey
 
ANALOG AND DIGITAL ELECTRONICS unit 5
ANALOG AND DIGITAL ELECTRONICS unit 5ANALOG AND DIGITAL ELECTRONICS unit 5
ANALOG AND DIGITAL ELECTRONICS unit 5
ACE ENGINEERING COLLEGE
 
Closed loop control of cascaded input dual active bridge converter for multip...
Closed loop control of cascaded input dual active bridge converter for multip...Closed loop control of cascaded input dual active bridge converter for multip...
Closed loop control of cascaded input dual active bridge converter for multip...
PERWEZ ALAM
 
QX Simulator and quantum programming - 2020-04-28
QX Simulator and quantum programming - 2020-04-28QX Simulator and quantum programming - 2020-04-28
QX Simulator and quantum programming - 2020-04-28
Aritra Sarkar
 
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-ChipOptimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
IDES Editor
 
Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...
Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...
Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...
Hsien-Hsin Sean Lee, Ph.D.
 
closing-the-hardware-design-loop-with-multisim-a-case-study
closing-the-hardware-design-loop-with-multisim-a-case-studyclosing-the-hardware-design-loop-with-multisim-a-case-study
closing-the-hardware-design-loop-with-multisim-a-case-studyAyush Bhardwaj
 
Iaetsd an mtcmos technique for optimizing low
Iaetsd an mtcmos technique for optimizing lowIaetsd an mtcmos technique for optimizing low
Iaetsd an mtcmos technique for optimizing low
Iaetsd Iaetsd
 
Block diagrams.ppt
Block diagrams.pptBlock diagrams.ppt
Block diagrams.ppt
nteziryayocelestin4
 
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...
Hardik Parikh, E.I.T.
 
Fuzzy motor
Fuzzy motorFuzzy motor
Fuzzy motor
Seyed Yahya Moradi
 
Sequential circuit-flip flops
Sequential circuit-flip flopsSequential circuit-flip flops
Sequential circuit-flip flops
Dr Naim R Kidwai
 
IJCER (www.ijceronline.com) International Journal of computational Engineeri...
 IJCER (www.ijceronline.com) International Journal of computational Engineeri... IJCER (www.ijceronline.com) International Journal of computational Engineeri...
IJCER (www.ijceronline.com) International Journal of computational Engineeri...ijceronline
 
Implementation of Linear Controller for a DC-DC Forward Converter
Implementation of Linear Controller for a DC-DC Forward ConverterImplementation of Linear Controller for a DC-DC Forward Converter
Implementation of Linear Controller for a DC-DC Forward Converter
ijceronline
 
Novelty Method of Speed Control Analysis of Permanent Magnet Brushless DC Motor
Novelty Method of Speed Control Analysis of Permanent Magnet Brushless DC MotorNovelty Method of Speed Control Analysis of Permanent Magnet Brushless DC Motor
Novelty Method of Speed Control Analysis of Permanent Magnet Brushless DC Motor
IRJET Journal
 
BIL406-Chapter-7-Superscalar and Superpipeline processors.ppt
BIL406-Chapter-7-Superscalar and Superpipeline  processors.pptBIL406-Chapter-7-Superscalar and Superpipeline  processors.ppt
BIL406-Chapter-7-Superscalar and Superpipeline processors.ppt
Kadri20
 
digital electronics Design of 101 sequence detector without overlapping for...
digital  electronics Design of 101 sequence detector without  overlapping for...digital  electronics Design of 101 sequence detector without  overlapping for...
digital electronics Design of 101 sequence detector without overlapping for...
sanjay kumar pediredla
 
AC Circuit Theory
AC Circuit TheoryAC Circuit Theory
AC Circuit Theory
AjEcuacion
 
Cse(b) g1 flipflop
Cse(b) g1 flipflopCse(b) g1 flipflop
Cse(b) g1 flipflop
KaranAgarwal71
 

Similar to presentation on pasta (20)

Extrapolation of Stage Discharge Rating Curve
Extrapolation of Stage Discharge Rating CurveExtrapolation of Stage Discharge Rating Curve
Extrapolation of Stage Discharge Rating Curve
 
ANALOG AND DIGITAL ELECTRONICS unit 5
ANALOG AND DIGITAL ELECTRONICS unit 5ANALOG AND DIGITAL ELECTRONICS unit 5
ANALOG AND DIGITAL ELECTRONICS unit 5
 
Closed loop control of cascaded input dual active bridge converter for multip...
Closed loop control of cascaded input dual active bridge converter for multip...Closed loop control of cascaded input dual active bridge converter for multip...
Closed loop control of cascaded input dual active bridge converter for multip...
 
QX Simulator and quantum programming - 2020-04-28
QX Simulator and quantum programming - 2020-04-28QX Simulator and quantum programming - 2020-04-28
QX Simulator and quantum programming - 2020-04-28
 
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-ChipOptimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
 
Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...
Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...
Lec14 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Se...
 
closing-the-hardware-design-loop-with-multisim-a-case-study
closing-the-hardware-design-loop-with-multisim-a-case-studyclosing-the-hardware-design-loop-with-multisim-a-case-study
closing-the-hardware-design-loop-with-multisim-a-case-study
 
Iaetsd an mtcmos technique for optimizing low
Iaetsd an mtcmos technique for optimizing lowIaetsd an mtcmos technique for optimizing low
Iaetsd an mtcmos technique for optimizing low
 
Block diagrams.ppt
Block diagrams.pptBlock diagrams.ppt
Block diagrams.ppt
 
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...
Design of a 3-phase FC-TCR Static Var Compensator for Power factor correction...
 
Fuzzy motor
Fuzzy motorFuzzy motor
Fuzzy motor
 
Sequential circuit-flip flops
Sequential circuit-flip flopsSequential circuit-flip flops
Sequential circuit-flip flops
 
IJCER (www.ijceronline.com) International Journal of computational Engineeri...
 IJCER (www.ijceronline.com) International Journal of computational Engineeri... IJCER (www.ijceronline.com) International Journal of computational Engineeri...
IJCER (www.ijceronline.com) International Journal of computational Engineeri...
 
Clock gating
Clock gatingClock gating
Clock gating
 
Implementation of Linear Controller for a DC-DC Forward Converter
Implementation of Linear Controller for a DC-DC Forward ConverterImplementation of Linear Controller for a DC-DC Forward Converter
Implementation of Linear Controller for a DC-DC Forward Converter
 
Novelty Method of Speed Control Analysis of Permanent Magnet Brushless DC Motor
Novelty Method of Speed Control Analysis of Permanent Magnet Brushless DC MotorNovelty Method of Speed Control Analysis of Permanent Magnet Brushless DC Motor
Novelty Method of Speed Control Analysis of Permanent Magnet Brushless DC Motor
 
BIL406-Chapter-7-Superscalar and Superpipeline processors.ppt
BIL406-Chapter-7-Superscalar and Superpipeline  processors.pptBIL406-Chapter-7-Superscalar and Superpipeline  processors.ppt
BIL406-Chapter-7-Superscalar and Superpipeline processors.ppt
 
digital electronics Design of 101 sequence detector without overlapping for...
digital  electronics Design of 101 sequence detector without  overlapping for...digital  electronics Design of 101 sequence detector without  overlapping for...
digital electronics Design of 101 sequence detector without overlapping for...
 
AC Circuit Theory
AC Circuit TheoryAC Circuit Theory
AC Circuit Theory
 
Cse(b) g1 flipflop
Cse(b) g1 flipflopCse(b) g1 flipflop
Cse(b) g1 flipflop
 

More from chendrashekar pabbaraju

Pasta documentation
Pasta  documentationPasta  documentation
Pasta documentation
chendrashekar pabbaraju
 
presentation on OLED
presentation on OLEDpresentation on OLED
presentation on OLED
chendrashekar pabbaraju
 
automation of railway gate using verilog, Documentation
automation of railway gate using verilog, Documentation  automation of railway gate using verilog, Documentation
automation of railway gate using verilog, Documentation
chendrashekar pabbaraju
 
wireless electricity seminar report
wireless electricity seminar reportwireless electricity seminar report
wireless electricity seminar report
chendrashekar pabbaraju
 
witricity academic seminar final year b.tech
witricity academic seminar final year b.tech witricity academic seminar final year b.tech
witricity academic seminar final year b.tech
chendrashekar pabbaraju
 
Automation of railway gate using verilog presentation
Automation of railway gate using verilog presentationAutomation of railway gate using verilog presentation
Automation of railway gate using verilog presentation
chendrashekar pabbaraju
 

More from chendrashekar pabbaraju (6)

Pasta documentation
Pasta  documentationPasta  documentation
Pasta documentation
 
presentation on OLED
presentation on OLEDpresentation on OLED
presentation on OLED
 
automation of railway gate using verilog, Documentation
automation of railway gate using verilog, Documentation  automation of railway gate using verilog, Documentation
automation of railway gate using verilog, Documentation
 
wireless electricity seminar report
wireless electricity seminar reportwireless electricity seminar report
wireless electricity seminar report
 
witricity academic seminar final year b.tech
witricity academic seminar final year b.tech witricity academic seminar final year b.tech
witricity academic seminar final year b.tech
 
Automation of railway gate using verilog presentation
Automation of railway gate using verilog presentationAutomation of railway gate using verilog presentation
Automation of railway gate using verilog presentation
 

Recently uploaded

RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
thanhdowork
 
Student information management system project report ii.pdf
Student information management system project report ii.pdfStudent information management system project report ii.pdf
Student information management system project report ii.pdf
Kamal Acharya
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Gen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdfGen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdf
gdsczhcet
 
AP LAB PPT.pdf ap lab ppt no title specific
AP LAB PPT.pdf ap lab ppt no title specificAP LAB PPT.pdf ap lab ppt no title specific
AP LAB PPT.pdf ap lab ppt no title specific
BrazilAccount1
 
MCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdfMCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdf
Osamah Alsalih
 
The Benefits and Techniques of Trenchless Pipe Repair.pdf
The Benefits and Techniques of Trenchless Pipe Repair.pdfThe Benefits and Techniques of Trenchless Pipe Repair.pdf
The Benefits and Techniques of Trenchless Pipe Repair.pdf
Pipe Restoration Solutions
 
Fundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptxFundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptx
manasideore6
 
CME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional ElectiveCME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional Elective
karthi keyan
 
Architectural Portfolio Sean Lockwood
Architectural Portfolio Sean LockwoodArchitectural Portfolio Sean Lockwood
Architectural Portfolio Sean Lockwood
seandesed
 
WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234
AafreenAbuthahir2
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Teleport Manpower Consultant
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
Divya Somashekar
 
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
ydteq
 
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxCFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
R&R Consult
 
Immunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary AttacksImmunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary Attacks
gerogepatton
 
English lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdfEnglish lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdf
BrazilAccount1
 
ethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.pptethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.ppt
Jayaprasanna4
 
Investor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptxInvestor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptx
AmarGB2
 
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
zwunae
 

Recently uploaded (20)

RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
 
Student information management system project report ii.pdf
Student information management system project report ii.pdfStudent information management system project report ii.pdf
Student information management system project report ii.pdf
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
 
Gen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdfGen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdf
 
AP LAB PPT.pdf ap lab ppt no title specific
AP LAB PPT.pdf ap lab ppt no title specificAP LAB PPT.pdf ap lab ppt no title specific
AP LAB PPT.pdf ap lab ppt no title specific
 
MCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdfMCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdf
 
The Benefits and Techniques of Trenchless Pipe Repair.pdf
The Benefits and Techniques of Trenchless Pipe Repair.pdfThe Benefits and Techniques of Trenchless Pipe Repair.pdf
The Benefits and Techniques of Trenchless Pipe Repair.pdf
 
Fundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptxFundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptx
 
CME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional ElectiveCME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional Elective
 
Architectural Portfolio Sean Lockwood
Architectural Portfolio Sean LockwoodArchitectural Portfolio Sean Lockwood
Architectural Portfolio Sean Lockwood
 
WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
 
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
 
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxCFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
 
Immunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary AttacksImmunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary Attacks
 
English lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdfEnglish lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdf
 
ethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.pptethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.ppt
 
Investor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptxInvestor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptx
 
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
 

presentation on pasta

  • 1. RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER By Ms. D.Vidya (14C35A0409) Ms. V.Pavanisujatha (13C31A04A1) Mr.P.Chendra shekar (13C31A0471) Under the guidance of Ms. M. Mounika Assistant professor BALAJI INSTITUTE OF TECHNOLOGYAND SCIENCE NARSAMPET, WARANGAL – 506 331 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
  • 2. CONTENT • INTRODUCTION • ABSTRACT • DESIGN OF PASTA • ARCHITECTURE OF PASTA • STATE DIAGRAMS FOR PASTA • FLOW CHART • RECURSIVE FORMULA FOR BINARY ADDITION • SIMULATION WAVE FORM FOR RECURSIVE ADDER • SYNTHESIS REPORT FOR RECURSIVE ADDER • APPLICATIONS • ADVANTAGES • CONCLUSION
  • 3. INTRODUCTION • Binary addition is the single most important operation that a processor performs. • Asynchronous circuits do not assume any quantization of time. • In principle, logic flow in asynchronous circuits is controlled by a request-acknowledgment handshaking protocol to establish a pipeline in the absence of clocks.
  • 4. ABSTRACT • It is based on a recursive formulation for performing multi-bit binary addition. • Do not need any carry chain propagation. • Does not have any practical limitations of high fan-outs. • A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel.
  • 5. DESIGN OF PASTA • The adder first accepts two input operands to perform half additions for each bit. • Subsequently, it iterates using earlier generated carry and sums to perform half-additions repeatedly until all carry bits are consumed and settled at zero level.
  • 7. Cont…. • Initially it select the actual operands during SEL = 0 and switch to feedback/carry paths for subsequent iterations using SEL = 1. • The feedback path from the HAs enables the multiple iterations to continue until the completion when all carry signals will assume zero values.
  • 9. Cont….. • During the initial phase, the circuit merely works as a combinational HA operating in fundamental mode. • During the iterative phase (SEL = 1), the feedback path through multiplexer block is activated. • The carry transitions (Ci ) are allowed as many times as needed to complete the recursion.
  • 11. Recursive Formula for Binary Addition • Sj i and Cj i+1 are the sum and carry for ith bit at the jth iteration. • The initial condition ( j = 0) for addition is formulated as follows: S0 I = ai ⊕ bi C0 i+1= ai bi .
  • 12. • The jth iteration for the recursive addition is formulated by Sj i = S j−1 i ⊕ C j−1 i , 0 ≤ i < n C j i+1 = S j−1 i C j−1 i , 0 ≤ i ≤ n. • The recursion is terminated at kth iteration when the following condition is met: Ck n + Ck n−1+ ・・ ・+Ck 1= 0, 0 ≤ k ≤ n.
  • 13. SIMULATION WAVE FORM FOR RECURSIVE ADDER
  • 14. SYNTHESIS REPORT FOR RECURSIVE ADDER
  • 15. APPLICATIONS • Digital systems designing • Digital signal processing • Multiplication and Accumulation • Arithmetic and Logic Unit (ALU) • Microprocessors
  • 16. ADVANTAGES • Delay will be reduced. • Area Efficient adders.
  • 17. CONCLUSION • The design achieves a very simple n-bit adder that is area and interconnection-wise equivalent to the simplest adder namely the RCA. • Moreover, the circuit works in a parallel manner for independent carry chains, and thus achieves logarithmic average time performance over random input values. • Simulation results are used to verify the advantages of the proposed approach.