The document details various aspects of VHDL, focusing on subprograms, packages, and their functionalities, including procedures and functions for code reuse. It explains how to declare and use packages, types, aliases, resolved signals, components, configurations, and concurrent statements. Additionally, it highlights the roles of simulation and synthesis in VHDL design, particularly with tools like the Aldec simulator and synthesis tools.

1. PRESENTATION MADE BY
KHUSHBOO JAIN

2. CONTENTS
 Subprograms
 Packages
 Use Clause
 Aliases
 Resolved Signals
 Components
 Configuration
 Generate Statements
 Concurrent statements
 Use of VHDL in Simulation and synthesis

3. SUBPROGRAMS
 Subprograms may exist as just a procedure body or
a function body.
 Subprograms may also have a procedure
declarations or a function declaration.
 Subprograms allows for code reuse and
simplification.
 Subprograms may also be used to reduce the
complexity of the programs.
 Mainly Subprograms of two types –
 Procedures
 Functions

4. Procedures
 Procedures are the subprograms that can generate
multiple outputs.
 Procedures can take input in form of parameters.
 To use the procedures there are two things :
o Procedure Declaration
o Procedure Body
SYNTAX: procedure declaration-
procedure identifier [ ( formal parameter list ) ] ;
procedure body-
procedure identifier [ ( formal parameter list ) ] is
begin
sequential statement(s)
end procedure identifier ;

5.  Example of procedure declaration
procedure build ( A : in integer;
B : inout signal bit_vector;
C : out real;
D : file ) ;
 Example of procedure declaration
procedure print_header is
begin
write ( my_line, string'("A B C"));
writeline ( output, my_line );
end procedure print_header ;

6. FUNCTION
The main difference between function and procedure
is that function can return only one value.
Functions must have a return value and return
statement and can’t modify the parameter passed to
them.
A caller statement must require for executing the
function.
SYNTAX: function declaration-
function identifier [ ( formal parameter list ) ] return a_type ;
Function body-
function identifier [ ( formal parameter list ) ]
return a_type is
Begin
sequential statement(s) return some_value; -- of type a_type
end function identifier ;

7.  Example of function declaration
function random return float ;
 Example of function declaration
function random return float is
begin
-- compute X
return X;
end function random ;

8. PACKAGES
 A VHDL PACKAGE contains subprograms,
constant definitions and type definitions to be
used throughout one or more design units.
 Package mechanism is a facility provided to
the developer so they can reuse their old code
and can save their time.
 Package mainly consists of 2 parts:
• Package declaration
• Package Body

9.  Package declaration format:
package package_name is
... exported constant declarations
... exported type declarations
... exported subprogram declarations
end package_name;
Example:
package ee530 is
constant maxint: integer := 16#ffff#;
type arith_mode_type is (signed, unsigned);
function minimum(constant a,b: in integer) return
integer;
end ee530;

10. Package body format:
package body package_name is
... exported subprogram bodies
... other internally-used declarations
end package_name;
Example:
package body ee530 is
function minimum (constant a,b: integer) return integer is variable c: integer; -- local
variable
Begin
if a < b then
c := a; -- a is min
else
c := b; -- b is min
end if;
return c;
-- return min value end;
end ee530;

11. USE clause
 Packages are made visible to a VHDL description
through the use of USE clause.
 This statement comes at the beginning of the
entity declaration or architecture body.
 The use clause makes visible items specified as
suffixes in selected names listed.
 SYNTAX: use library_name.package_name.item;
 EXAMPLE: use ieee.std_logic_1164.all;

12. ALIASES
 The alias declares an alternative name for any
existing objects, signal, variable ,constant or
file.
 Alias doesnot define a new object.
 It is just a specifc name assigned to some
existing objects.
 SYNTAX
alias alias_name : alias_type is object_name
 EXAMPLE
alias SIGN : bit is DATA(31);

13. RESOLVED SIGNALS
 When more than one input is connected to a
signal, the simulator has to figure out what to do.
If you send different signals in either
input, something has to come out the other side,
but what?
 The process of deciding this is called resolution.
A signal type that knows how to do this is called
a resolved signal.
 For each resolved signal the designer has to
specify an associated resolution function.
 The resolution function name is the name of a
function previously defined.

14. Resolution of processes
 The tricky thing is when you have one entity with
multiple processes. VHDL imagines each process as a
separate circuit. So, if you have two different
processes that each set the value of the signal T
somewhere, the simulator think of this situation.
 When this situtation comes up, it needs to do signal
resolution. This can cause unexpected results. For
example, this model has two processes that set the
signal T, so we run into the resolution problem. The
output is 'X' for most of the simulation.

15. COMPONENTS
 A component represents an entity/architecture pair.
 The component can be defined in package, entity,
architecture, or block declarations.
 A more universal approach is to declare a
component in the package.
 Generics and ports of a component are copies of
generics and ports of the entity the component
represents.
 SYNTAX
component component_name [ is ]
generic (generic_list);
port (port_list);
end component component_name;

16. Example of components
architecture STRUCTURE_2 of EXAMPLE is
component XOR_4 is
port(A,B: in BIT_VECTOR(0 to 3);
C: out BIT_VECTOR(0 to 3));
end component XOR_4;
signal S1,S2 : BIT_VECTOR(0 to 3);
signal S3 : BIT_VECTOR(0 to 3);
begin
X1 : XOR_4 port map(S1,S2,S3);
end architecture STRUCTURE_2;

17. CONFIGURATION
 A configuration is a construct that defines how
component instances in a given block are bound to
design entities in order to describe how design
entities are put together to form a complete design.
 The configuration declaration starts with the
configuration name and then it is associated to a
given design entity
 Declarative part of the configuration may contain use
clauses, attribute specifications and group
declarations. The main part of the configuration
declaration contains so called block configuration.

18. SYNTAX -
configuration configuration_name of entity_name is
for architecture_name
for instance_label:component_name
use entity library_name.entity_name(arch_name);
end for;
end for;
end [configuration] [configuration_name];
EXAMPLE -
configuration Conf_Test of Test is
for STRUCTURE_T
for T_1 : DEC use configuration CONF_E;
end for;
end for;
end configuration Conf_Test;

19. STATEMENTS
 The generate statement simplifies description of
regular design structures.
 Usually it is used to specify a group of identical
components using just one component specification
and repeating it using the generate mechanism.
 A generate statement consists of three main parts:
1. generation scheme (either for scheme or if scheme);
2. declarative part.
3. concurrent statements.
 The for generation scheme is used to describe regular
structures in the design.
 It is quite common that regular structures contain
some irregularities. In such cases, the if scheme is
very useful.

20.  SYNTAX of FOR scheme
label : for parameter in range generate
[ { declarations }
begin ]
{ concurrent_statements }
end generate [ label ] ;
 SYNTAX of IF scheme
label : if condition generate
[ { declarations }
begin ]
{ concurrent_statements }
end generate [ label ] ;

21. CONCURRENT
STATEMENTS
 Concurrent statements provide convenient syntax for
representing simple, commonly occurring forms of
processes, as well as regular descriptions.
 CONCURRENT SIGNAL ASSIGNMENT
STATEMENT –
represents an equivalent process statement that
assigns values to signals.
SYNTAX-
concurrent_signal_assignment_statement ::= [ label : ]
conditional_signal_assignment [ label : ]
selected_signal_assignment

22. CONDITIONAL SIGNAL ASSIGNMENT
represents a process statement in which the signal
transform is an if statement.
SYNTAX-
Conditional_signal_assignment ::= target <= options
conditional_waveforms ;
Conditional_waveforms ::= { waveform when condition
else } waveform [ when condition ];
SELECTED SIGNAL ASSIGNMENT
represents a process statement in which the signal
transform is a case statement.
SYNTAX-
selected_signal_assignment ::= with expression select
target <= options selected_waveforms;
selected_waveforms ::= { waveform when choices , }
waveform when choices

23. USE OF VHDL IN SIMULATION
AND SYNTHESIS
 Simulation is the execution of a model in the
software environment. This is done using the ALDEC
VHDL simulator.
 Test bench is a program whose purpose is to
verify that the behavior of our system is as expected.
The test bench is used in ALDEC to simulate our
design by specifying the inputs into the system.
 Synthesis is the process of translating a design
description to another level of abstraction, i.e, from
behaviour to structure. We achieved synthesis by
using a Synthesis tool like Foundation Express .It is
similar to the compilation of a high level