This document compares different watermarking schemes (Spread Spectrum, Scalar Costa scheme Quantization Index Modulation, and Rational Dither Modulation) and encryption techniques (RC4, RC5, RC6) for securing JPEG2000 images. It finds that RC5 is more secure than RC4 due to more rounds, and RC6 is used instead of RC5 due to greater use of registers. The watermarking schemes provide robustness while the encryption techniques secure the images for copyright protection and content authentication. Peak signal-to-noise ratio and mean square error are compared for different watermarked images.
Watermarking of JPEG2000 Compressed Images with Improved EncryptionEditor IJCATR
The need for copyright protection, ownership verification, and other issues for digital data are getting more and more interest nowadays. Among the solutions for these issues, digital watermarking techniques are used. A range of watermarking methods has been projected. Compression plays a foremost role in the design of watermarking algorithms. For a digital watermarking method to be effective, it is vital that an embedded watermark should be robust against compression. JPEG2000 is a new standard for image compression and transmission. JPEG2000 offers both lossy and lossless compression. The projected approach is used to execute a robust watermarking algorithm to watermark JPEG2000 compressed and encrypted images. For encryption it uses RC6 block cipher. The method embeds watermark in the compressed- encrypted domain and extraction is done in the decrypted domain. The proposal also preserves the confidentiality of substance as the embedding is done on encrypted data. On the whole 3 watermarking schemes are used: Spread Spectrum, Scalar Costa Scheme Quantization Index Modulation, and Rational Dither Modulation.
Performance Study of BCH Error Correcting Codes Using the Bit Error Rate Term...IJERA Editor
The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
In OFDM-IDMA scheme, intersymbol interference (ISI) is resolved by the OFDM layer and multiple access interference (MAI) is suppressed by the IDMA layer at low cost . However OFDM-IDMA scheme suffers high peakto-average power ratio (PAPR) problem. For removing high PAPR problem a hybrid multiple access scheme SC-FDM-IDMA has been proposed. In this paper, bit error rate (BER) performance comparison of SC-FDM-IDMA scheme, OFDM-IDMA scheme and IDMA scheme have been duly presented. Moreover, the BER performance of various subcarrier mapping methods for SC-FDM-IDMA scheme as well as other results with variation of different parameters have also been demonstrated. Finally simulation result for BER performance improvement has been shown employing BCH code. All the simulation results demonstrate the suitability of SC-FDMIDMA scheme for wireless communication under AWGN channel environment.
Modified Golomb Code For Integer RepresentationIJSRD
In this computer age, all the computer applications handle data in the form of text, numbers, symbols and combination of all of them. The primary objective of data compression is to reduce the size of data while data needs to be stored and transmitted in the digital devices. Hence, the data compression plays a vital role in the areas of data storage and data transmission. Golomb code, which is a variable-length integer code, has been used for text compression, image compression, video compression and audio compression. The drawback of Golomb code is that it requires more bits to represent large integers if the divisor is small. Alternatively, Golomb code needs more bits to represent small integers if the divisor is large. This paper proposes Modified Golomb Code based on Golomb Code, Extended Golomb Code to represent small as well as large integers compactly for the chosen divisor. In this work, as an application of Modified Golomb Code, Modified Golomb Code is used with Burrows-Wheeler transform for text compression. The performances of Golomb Code and Modified Golomb Code are evaluated on Calcary corpus dataset. The experimental results show that the proposed code provides better compression rate than Golomb code on an average. The performance of the proposed code is also compared with Extended Golomb Codes (EGC). The comparison results show that the proposed code achieves significant improvement for the binary files of Calgary corpus comparing to EGC.
An Efficient Interpolation-Based Chase BCH Decoderijsrd.com
Error correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. Bose,Ray Chaudhuri, Hocquenghem (BCH)codes are one of the error correcting codes. The BCH decoder consists of four blocks namely syndrome block, chien search block and error correction block. This paper describes a new method for error detection in syndrome and chien search block of BCH decoder. The proposed syndrome block is used to reduce the number of computation by calculating the even number syndromes from the corresponding odd number syndromes.
Watermarking of JPEG2000 Compressed Images with Improved EncryptionEditor IJCATR
The need for copyright protection, ownership verification, and other issues for digital data are getting more and more interest nowadays. Among the solutions for these issues, digital watermarking techniques are used. A range of watermarking methods has been projected. Compression plays a foremost role in the design of watermarking algorithms. For a digital watermarking method to be effective, it is vital that an embedded watermark should be robust against compression. JPEG2000 is a new standard for image compression and transmission. JPEG2000 offers both lossy and lossless compression. The projected approach is used to execute a robust watermarking algorithm to watermark JPEG2000 compressed and encrypted images. For encryption it uses RC6 block cipher. The method embeds watermark in the compressed- encrypted domain and extraction is done in the decrypted domain. The proposal also preserves the confidentiality of substance as the embedding is done on encrypted data. On the whole 3 watermarking schemes are used: Spread Spectrum, Scalar Costa Scheme Quantization Index Modulation, and Rational Dither Modulation.
Performance Study of BCH Error Correcting Codes Using the Bit Error Rate Term...IJERA Editor
The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
In OFDM-IDMA scheme, intersymbol interference (ISI) is resolved by the OFDM layer and multiple access interference (MAI) is suppressed by the IDMA layer at low cost . However OFDM-IDMA scheme suffers high peakto-average power ratio (PAPR) problem. For removing high PAPR problem a hybrid multiple access scheme SC-FDM-IDMA has been proposed. In this paper, bit error rate (BER) performance comparison of SC-FDM-IDMA scheme, OFDM-IDMA scheme and IDMA scheme have been duly presented. Moreover, the BER performance of various subcarrier mapping methods for SC-FDM-IDMA scheme as well as other results with variation of different parameters have also been demonstrated. Finally simulation result for BER performance improvement has been shown employing BCH code. All the simulation results demonstrate the suitability of SC-FDMIDMA scheme for wireless communication under AWGN channel environment.
Modified Golomb Code For Integer RepresentationIJSRD
In this computer age, all the computer applications handle data in the form of text, numbers, symbols and combination of all of them. The primary objective of data compression is to reduce the size of data while data needs to be stored and transmitted in the digital devices. Hence, the data compression plays a vital role in the areas of data storage and data transmission. Golomb code, which is a variable-length integer code, has been used for text compression, image compression, video compression and audio compression. The drawback of Golomb code is that it requires more bits to represent large integers if the divisor is small. Alternatively, Golomb code needs more bits to represent small integers if the divisor is large. This paper proposes Modified Golomb Code based on Golomb Code, Extended Golomb Code to represent small as well as large integers compactly for the chosen divisor. In this work, as an application of Modified Golomb Code, Modified Golomb Code is used with Burrows-Wheeler transform for text compression. The performances of Golomb Code and Modified Golomb Code are evaluated on Calcary corpus dataset. The experimental results show that the proposed code provides better compression rate than Golomb code on an average. The performance of the proposed code is also compared with Extended Golomb Codes (EGC). The comparison results show that the proposed code achieves significant improvement for the binary files of Calgary corpus comparing to EGC.
An Efficient Interpolation-Based Chase BCH Decoderijsrd.com
Error correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. Bose,Ray Chaudhuri, Hocquenghem (BCH)codes are one of the error correcting codes. The BCH decoder consists of four blocks namely syndrome block, chien search block and error correction block. This paper describes a new method for error detection in syndrome and chien search block of BCH decoder. The proposed syndrome block is used to reduce the number of computation by calculating the even number syndromes from the corresponding odd number syndromes.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Performance Improved Multipliers Based on Non-Redundant Radix-4 Signed-Digit ...IJMTST Journal
In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {1; 0; +1; +2} or {-2; -1; 0; +1}, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
In this presentation we consider several main methods for contruction regular QC-LDPC codes using algebraic approach. Consider existance of non broken by circulant permutation matrix cycles (short balanced cycles). Using Vontobel approach illustrate way to estimate girth bound and it influence on error-floor properties of QC-LDPC codes
Comparison of Turbo Codes and Low Density Parity Check CodesIOSR Journals
Abstract-The most powerful channel coding schemes, namely, those based on turbo codes and LPDC (Low density parity check) codes have in common principle of iterative decoding. Shannon’s predictions for optimal codes would imply random like codes, intuitively implying that the decoding operation on these codes would be prohibitively complex. A brief comparison of Turbo codes and LDPC codes will be given in this section, both in term of performance and complexity. In order to give a fair comparison of the codes, we use codes of the same input word length when comparing. The rate of both codes is R = 1/2. However, the Berrou’s coding scheme could be constructed by combining two or more simple codes. These codes could then be decoded separately, whilst exchanging probabilistic, or uncertainty, information about the quality of the decoding of each bit to each other. This implied that complex codes had now become practical. This discovery triggered a series of new, focused research programmes, and prominent researchers devoted their time to this new area.. Leading on from the work from Turbo codes, MacKay at the University of Cambridge revisited some 35 year old work originally undertaken by Gallagher [5], who had constructed a class of codes dubbed Low Density Parity Check (LDPC) codes. Building on the increased understanding on iterative decoding and probability propagation on graphs that led on from the work on Turbo codes, MacKay could now show that Low Density Parity Check (LDPC) codes could be decoded in a similar manner to Turbo codes, and may actually be able to beat the Turbo codes [6]. As a review, this paper will consider both these classes of codes, and compare the performance and the complexity of these codes. A description of both classes of codes will be given.
FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID ...VLSICS Design
The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.
Low complexity video coding for sensor networkeSAT Journals
Abstract Modern video codecs such as H.264/AVC give state-of-the-art compression performance. However, extensive use of optimization tools makes them highly complex and hence not suitable for wireless video sensor network. In this paper an efficient video codec with substantially reduced complexity is proposed. Simulation result shows that the proposed video codec gives comparable compression performance compared to H.264/AVC but at substantially reduced computational complexity. Keywords—Low complexity coding, Sensor network, Video coding, Wavelet transform.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient implementation of bit parallel finite field multiplierseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient implementation of bit parallel finite eSAT Journals
Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
FURTHER RESULTS ON THE DIRAC DELTA APPROXIMATION AND THE MOMENT GENERATING FU...IJCNC
In this article, we employ two distinct methods to derive simple closed-form approximations for the
statistical expectations of the positive integer powers of Gaussian probability integral Eg [Qp ( bWg )]
with
respect to its fading signal-to-noise ratio (SNR) g random variable. In the first approach, we utilize the
shifting property of Dirac delta function on three tight bounds/approximations for Q(.) to circumvent the
need for integration.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
Intra Frame Coding in H.264 to Obtain Consistent PSNR and Reduce Bit Rate for...RSIS International
In this paper developed a better approach for Intra frame coding in advanced video coding standard for vertical right intra prediction mode using Gaussian pulse to achieve better coding efficiency interms of picture quality, bit rate and encoding time. Intra prediction of advanced video coding standard used to code Intra frame to achieve better coding efficiency The proposed algorithm is based on Gaussian pulse which avoids intermixing of frequency samples which give the resulting signal in reversible form and achieve reduced bit rate for higher values of quantization parameters. MATLAB soft tool were used to implement proposed algorithm and compared with original JM18.6 reference algorithm of H.264. The results of proposed algorithm are compared with previous algorithm Pengyu et al. The simulation results of the proposed algorithm achieved less loss in PSNR and reduced in bit rate of 17.00% for QCIF sequences in vertical right intra prediction mode using Gaussian pulse compared with previous algorithm Pengyu et al..
Conferencia: Arquitectura Sustentable y Construcciones sustentables del Dr. Ing. Arq. Jorge Daniel Czajkowski,
Profesor Universidad Nacional de La Plata e Investigador CONICET. En XIII Congreso Argentino de Petroquímica. Organizado por IPA- Instituto Petroquímico Argentino. Buenos Aires, 14 y 15 junio 2016.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Performance Improved Multipliers Based on Non-Redundant Radix-4 Signed-Digit ...IJMTST Journal
In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {1; 0; +1; +2} or {-2; -1; 0; +1}, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
In this presentation we consider several main methods for contruction regular QC-LDPC codes using algebraic approach. Consider existance of non broken by circulant permutation matrix cycles (short balanced cycles). Using Vontobel approach illustrate way to estimate girth bound and it influence on error-floor properties of QC-LDPC codes
Comparison of Turbo Codes and Low Density Parity Check CodesIOSR Journals
Abstract-The most powerful channel coding schemes, namely, those based on turbo codes and LPDC (Low density parity check) codes have in common principle of iterative decoding. Shannon’s predictions for optimal codes would imply random like codes, intuitively implying that the decoding operation on these codes would be prohibitively complex. A brief comparison of Turbo codes and LDPC codes will be given in this section, both in term of performance and complexity. In order to give a fair comparison of the codes, we use codes of the same input word length when comparing. The rate of both codes is R = 1/2. However, the Berrou’s coding scheme could be constructed by combining two or more simple codes. These codes could then be decoded separately, whilst exchanging probabilistic, or uncertainty, information about the quality of the decoding of each bit to each other. This implied that complex codes had now become practical. This discovery triggered a series of new, focused research programmes, and prominent researchers devoted their time to this new area.. Leading on from the work from Turbo codes, MacKay at the University of Cambridge revisited some 35 year old work originally undertaken by Gallagher [5], who had constructed a class of codes dubbed Low Density Parity Check (LDPC) codes. Building on the increased understanding on iterative decoding and probability propagation on graphs that led on from the work on Turbo codes, MacKay could now show that Low Density Parity Check (LDPC) codes could be decoded in a similar manner to Turbo codes, and may actually be able to beat the Turbo codes [6]. As a review, this paper will consider both these classes of codes, and compare the performance and the complexity of these codes. A description of both classes of codes will be given.
FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID ...VLSICS Design
The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.
Low complexity video coding for sensor networkeSAT Journals
Abstract Modern video codecs such as H.264/AVC give state-of-the-art compression performance. However, extensive use of optimization tools makes them highly complex and hence not suitable for wireless video sensor network. In this paper an efficient video codec with substantially reduced complexity is proposed. Simulation result shows that the proposed video codec gives comparable compression performance compared to H.264/AVC but at substantially reduced computational complexity. Keywords—Low complexity coding, Sensor network, Video coding, Wavelet transform.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient implementation of bit parallel finite field multiplierseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient implementation of bit parallel finite eSAT Journals
Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
FURTHER RESULTS ON THE DIRAC DELTA APPROXIMATION AND THE MOMENT GENERATING FU...IJCNC
In this article, we employ two distinct methods to derive simple closed-form approximations for the
statistical expectations of the positive integer powers of Gaussian probability integral Eg [Qp ( bWg )]
with
respect to its fading signal-to-noise ratio (SNR) g random variable. In the first approach, we utilize the
shifting property of Dirac delta function on three tight bounds/approximations for Q(.) to circumvent the
need for integration.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
Intra Frame Coding in H.264 to Obtain Consistent PSNR and Reduce Bit Rate for...RSIS International
In this paper developed a better approach for Intra frame coding in advanced video coding standard for vertical right intra prediction mode using Gaussian pulse to achieve better coding efficiency interms of picture quality, bit rate and encoding time. Intra prediction of advanced video coding standard used to code Intra frame to achieve better coding efficiency The proposed algorithm is based on Gaussian pulse which avoids intermixing of frequency samples which give the resulting signal in reversible form and achieve reduced bit rate for higher values of quantization parameters. MATLAB soft tool were used to implement proposed algorithm and compared with original JM18.6 reference algorithm of H.264. The results of proposed algorithm are compared with previous algorithm Pengyu et al. The simulation results of the proposed algorithm achieved less loss in PSNR and reduced in bit rate of 17.00% for QCIF sequences in vertical right intra prediction mode using Gaussian pulse compared with previous algorithm Pengyu et al..
Conferencia: Arquitectura Sustentable y Construcciones sustentables del Dr. Ing. Arq. Jorge Daniel Czajkowski,
Profesor Universidad Nacional de La Plata e Investigador CONICET. En XIII Congreso Argentino de Petroquímica. Organizado por IPA- Instituto Petroquímico Argentino. Buenos Aires, 14 y 15 junio 2016.
DIGITAL IMAGE WATERMARKING OF COMPRESSED IMAGE USING JPEG 2000 AND ENCRYPTION...ijiert bestjournal
The necessity for copyright protection,ownership v erification,and other issues for digital data are getting more and more value these days. For the rap id revolution in digital multimedia and the ease of creating similar and unauthorized data,the digital data can be copied or manipulated or distributed. So it is necessary to watermark the media content for tamper proofing or quality assessment or copy control. In this paper we propose a JPEG2000 compre ssion. The compression standard is chosen such that it provides higher compression ratio and the c ompressed byte stream are randomized by the encryption algorithm. In our paper watermarking was done in the compressed � encrypted domain. We use different watermarking techniques for this. Att empting to watermark such a randomized bit stream can cause a dramatic degradation of the media quali ty. Thus it is necessary to choose an encryption scheme that is both secure and will allow watermark ing in a predictable manner in the compressed encrypted domain. The projected method is a robust watermarking algorithm to watermark JPEG2000 compressed and encrypted images (grayscale) of size 512�512. The encryption algorithm in this paper uses stream cipher. While the estimated technique e mbeds watermark in the compressed-encrypted domain,and the extraction of watermark can be done in the encrypted domain. The proposed algorithm also conserves the confidentiality of data as the e mbedding process can be done on encrypted data.
Chaos Encryption and Coding for Image Transmission over Noisy Channelsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
An efficient reconfigurable code rate cooperative low-density parity check co...IJECEIAES
In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz.
Low complexity design of non binary ldpc decoder using extended min-sum algor...eSAT Journals
Abstract
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon’s limit. Nonbinary
LDPC is the class of binary LDPC, which works on the higher order Galois field. The decoding performance of non-binary
(NB) LDPC is better than binary LDPC for moderate code lengths. The increased computation with the increased order of field is
the major challenge in hardware realization of NB-LDPC. The extension of conventional sum-product algorithm, known as
extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper. However, a tradeoff exists
between computational complexity and decoding performance.
This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The
bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm
can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
Keywords—Non-binary; LDPC; EMS algorithm; PCM
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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Evaluation and Analysis of Rate Control Methods for H.264/AVC and MPEG-4 Vide...IJECEIAES
Audio, image and video signals produce a vast amount of data. The only solution of this problem is to compress data before storage and transmission. In general there is the three crucial terms as, Bit Rate Reduction, Fast Data Transfer and Reduction in Storage. Rate control is a vigorous factor in video coding. In video communications, rate control must ensure the coded bitstream can be transmitted effectively and make full use of the narrow bandwidth. There are various test models usually suggested by a standard during the development of video codes models in order to video coding which should be suffienciently be efficient based on H.264 at very low bit rate. These models are Test Model Number 5 (TMN5), Test Model Number 8 for H.263, and Verification Model 8 (VM8) for MPEG-4 and H.264 etc. In this work, Rate control analysis for H.264, MPEG-4 performed. For Rate control analysis test model verification model version 8.0 is adopted.
LDPC Encoding and Hamming Encoding using MATLAB.
An LDPC code is a linear block code characterised by a very sparse parity-check matrix. This means that the parity check matrix has a very low concentration of 1’s in it, hence the name is “low-density parity-check” code. The sparseness of LDPC codes is what as it can lead to excellent performance in terms of bit error rates.
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