Novel design algorithm for low complexity programmable fir filters based on extended double base number system

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NOVEL DESIGN ALGORITHM FOR LOW COMPLEXITY PROGRAMMABLE FIR
FILTERS BASED ON EXTENDED DOUBLE BASE NUMBER SYSTEM
ABSTRACT
Coefficient multipliers are the stumbling blocks in programmable finite impulse response
(FIR) digital filters. As the filter coefficients change either dynamically or periodically, the
search for common sub-expressions for multi pliers less implementation needs to be performed
over the entire gamut of integers of the desired precision, and the amount of shifts associated
with each identified common sub-expression needs to be memorized. The complexity of a
quality search is thus beyond the existing design algorithms based on conventional binary and
signed digit representations. This paper presents a new design paradigm for the programmable
FIR filters by exploiting the extended double base number system (EDBNS). Due to its sparsity
and innate abstraction of the sum of binary shifted partial products, the sharing of adders in the
time-multiplexed multiple constant multiplication block of the programmable FIR filters can be
maximized by a direct mapping from the quasi-minimum EDBNS. The multiplexing cost can be
further reduced by merging double base terms. Logic synthesis results on more than one hundred
programmable filters with filter taps ranging from 10 to 100 and coefficient word lengths of 8,
12, and 16 bits show that the average logic complexity and critical path delay of the
programmable FIR filters designed by our proposed algorithm have been reduced by up to
47.81% and 14.32%, respectively over the existing design methods.

PhoenixIndia Technologies presents a novel algorithm for designing low complexity programmable FIR filters based on an extended double base number system. The algorithm exploits the sparsity and abstraction of the sum of binary shifted partial products in the extended double base number system to maximize sharing of adders in the time-multiplexed constant multiplication block of programmable FIR filters. Logic synthesis results on over 100 programmable FIR filters show the algorithm reduces average logic complexity by up to 47.81% and critical path delay by up to 14.32% compared to existing design methods.

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Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance. Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline

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Chennai Office: JP INFOTECH, Old No.31, New No.86, 1st Floor, 1st Avenue, Ashok Nagar, Chennai-83. Landmark: Next to Kotak Mahendra Bank/Bharath Scans Landline: (044) - 43012642 / Mobile: (0)9952649690 Pondicherry Office: JP INFOTECH, #45, Kamaraj Salai, Thattanchavady, Puducherry - 9 Landmark: Opp. to Thattanchavady Industrial Estate & Next to VVP Nagar Arch. Landline: (0413) - 4300535 / Mobile: (0)8608600246 / (0)9952649690

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This document describes a novel algorithm for designing low complexity programmable FIR filters based on an extended double base number system. The algorithm aims to maximize the sharing of adders in the filter's time-multiplexed constant multiplication block by directly mapping coefficients to a quasi-minimum extended double base number system representation. This provides more efficient implementation of coefficient multipliers, which are otherwise complex parts of programmable FIR filters. Logic synthesis results on over 100 filters showed the algorithm reduced logic complexity by up to 47.81% and critical path delay by up to 14.32% compared to existing design methods. The document also provides contact information for Logic Mind Technologies in Bangalore, India regarding the project flow and hardware/software requirements.

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