This document describes a proposed efficient constant multiplier architecture based on a vertical-horizontal binary common sub-expression elimination algorithm for designing reconfigurable finite impulse response filters with dynamically changing coefficients. The algorithm first applies a 2-bit binary common sub-expression elimination vertically across adjacent coefficients, then horizontally within each coefficient. Implementation results show the algorithm reduces average power consumption by 32-52% and improves the area power product by 25-66% compared to existing algorithms. For finite impulse response filter implementation, the algorithm achieves improvements of 13-28% in area delay product and 76.1-77.8% in power delay product over previous multiple constant multiplication algorithms.

1. Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
An Efficient Constant Multiplier Architecture
Based on Vertical-Horizontal Binary Common
Sub-expression Elimination Algorithm for
Reconfigurable FIR Filter Synthesis
Abstract—This paper proposes an efficient constant multiplierarchitecture based
on vertical-horizontal binary commonsub-expression elimination (VHBCSE)
algorithm for designing a reconfigurable finite impulse response (FIR) filter whose
coefficients can dynamically change in real time. To design an efficient
reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit
binary common sub-expression elimination (BCSE) algorithm has been applied
vertically across adjacentcoefficients on the 2-D space of the coefficient matrix
initially, followed by applying variable-bit BCSE algorithm horizontally within
each coefficient. This technique is capable of reducing the average probability of
use or the switching activity of the multiplier block adders by 6.2% and 19.6% as
compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively.
ASIC implementation results of FIR filters using this multiplier show that the
proposed VHBCSE algorithm is also successful in reducing the average power
consumption by 32% and 52% along with an improvement in the area power
product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE
algorithms respectively. As regards the implementation of FIR filter,
improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8%

2. in power delay product (PDP) for the proposed VHBCSE algorithm have been
achieved over those of the earlier multiple constant multiplication (MCM)
algorithms, viz. faithfully rounded truncated multiple constant
multiplication/accumulation (MCMAT) and multi-root binary partition graph
(MBPG) respectively. Efficiency shown by the results of comparing the FPGA and
ASIC implementations of the reconfigurable FIR filter designed using VHBCSE
algorithm based constant multiplier establishes the suitability of the proposed
algorithm for efficient fixed point reconfigurable FIR filter synthesis.
SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com