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Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
A High-Performance FIR Filter Architecture for
Fixed and Reconfigurable Applications
Abstract—Transpose form finite-impulse response (FIR) filters are inherently
pipelined and support multiple constant multiplications (MCM) technique
that results in significant saving of computation. However, transpose form
configuration does not directly support the block processing unlike directform
configuration. In this paper, we explore the possibility of realization of block
FIR filter in transpose form configuration for area-delay efficient realization
of large order FIR filters for both fixed and reconfigurable applications.
Basedon a detailed computational analysis of transpose form configuration of
FIR filter, we have derived a flow graph for transpose form block FIR filter
with optimized register complexity. A generalized block formulation is
presented for transpose form FIR filter. We have derived a general
multiplier-based architecture for the proposed transpose form block filter for
reconfigurable applications. A low-complexity design using the MCM scheme
is also presented for the block implementation of fixed FIR filters. The
proposed structure involves significantly less areadelay product (ADP) and
less energyper sample (EPS)than the existing block implementation of direct-
form structure for medium or large filter lengths, while for the short-length
filters, the block implementation of direct-form FIR structure has less ADP
and less EPS than the proposed structure. Applicationspecific integrated
circuit synthesis result shows that the proposed structure for block size 4 and
filter length 64 involves 42% less ADP and 40% less EPS than the best
available FIR filter structure proposed for reconfigurable applications. For
the same filter length and the same block size, the proposed structure involves
13% less ADP and 12.8%less EPS than that of the existing direct-form block
FIR structure.
SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com
A high performance fir filter architecture for

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A high performance fir filter architecture for

  • 1. Logic Mind Technologies Vijayangar (Near Maruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Abstract—Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike directform configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Basedon a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less areadelay product (ADP) and less energyper sample (EPS)than the existing block implementation of direct- form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. Applicationspecific integrated circuit synthesis result shows that the proposed structure for block size 4 and
  • 2. filter length 64 involves 42% less ADP and 40% less EPS than the best available FIR filter structure proposed for reconfigurable applications. For the same filter length and the same block size, the proposed structure involves 13% less ADP and 12.8%less EPS than that of the existing direct-form block FIR structure. SOFTWARE REQUIREMENT:  ModelSim6.4c.  Xilinx 9.1/13.2. HARDWARE REQUIREMENT:  FPGA Spartan 3. PROJECT FLOW: First Review: Literature Survey Paper Explanation Design of Project Project Enhancement explanation Second Review: Implementing 40% of Base Paper Third Review Implementing Remaining 60% of Base Paper with Future Enhancement (Modification) For More Details please contact Logic Mind Technologies Vijayangar (NearMaruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Mail: logicmindtech@gmail.com