1. SHRUTHI RENGANATHA DESIGAN
7720, McCallum Blvd, Apt #2045 Dallas, Texas-75252 Mobile+1(469)951-9309
https://www.linkedin.com/in/shruthidesigan Email shruthidesigan09@gmail.com
OBJECTIVE
Actively Seeking Co-op/Internship for Fall 2016/Spring 2017 in SoC Validation/Verification/Physical Design/ASIC Design.
EDUCATION
Master’s in Electrical Engineering (Digital System) CGPA:3.568
The University of Texas at Dallas, Richardson, TX Spring’17-Anticipated
Coursework- VLSI, Computer Architecture, Microprocessor Systems, RF and Microwave Systems Engineering, Advanced
Digital Logic, Advanced Computer Networks.
Bachelors in Electronics and Communication Engineering CGPA:8.0/10
Anna University, Chennai, India (Aug’10-May’14)
INTERNSHIP EXPERIENCE
Post-Silicon SoC Validation Intern at QUALCOMM (May’16-July’16)
 Worked with System on Chip(SoC) Validation and Emulation team on Qualcomm’s next generation chip–Snapdragon
600 series processor in its Post-Silicon stage, validating on an ASIC prototype (Chip Development Platform) to
automate the measurement of minimum voltage for processors based on frequency.
 Developed an automated scheduled routine to verify the functionality of blocks which reduced the manual execution
time by 50%.
TECHNICAL SKILLS
Cadence : Virtuoso Design Suite, Assura, Encounter APR.
Synopsys Tools : Design Compiler, Tetramax, X-start, HSpice, Silicon Smart ACE
Design Tools : Xilinx ISE Design suite, Matlab, CPLEX, AWR (VSS Simulator)
Programming Languages : Verilog, VHDL, C++, C.
Scripting Language : Perl, Shell, Python.
Hardware : 8085, 8086,8051, MSP430 Microcontroller, ARM Cortex M3, Trace 32.
Operating Systems : Windows, UNIX, LINUX.
GRADUATE ACADEMIC PROJECT
Trivium Cipher- Widely used Cryptographic primitive, IBM 130nm Technology (Feb’16-May’16)
 Designed a synchronous stream cipher with 288-bit internal state containing three Nonlinear feedback shift registers.
It uses 305 cells and produces 3 bits change in the state and one bit change in secret key after every 288 clock cycle.
 Video link of my Project: https://www.youtube.com/watch?v=Ux8SO7g9T4U
Stop Watch in Nexys 3 Spartan -6 FPGA Board (Mar’16-May’16)
 Implemented Stop watch on Nexys 3 Spartan with 1 switch and 2 buttons as an input- Switch is used to adjust seconds
and minutes; Reset and pause button are used to control the state of the Stopwatch.
Cache Memory Design (Sep’15-Oct’15)
 Designed an optimum memory configuration for an Alpha 21264 processor by fine tuning the cache hierarchy which
involves analysis on parameters such as Associativity, Cache size, Cache level and Replacement policy. This is
performed on three benchmarks-GO, Anagram and GCC. Cycles per Instruction (CPI) and cost values are obtained
to comment on the trade–off between design choice and cost.
Effect of Branch Predictors in Alpha 21264 (Oct’15-Nov’15)
 Studied the effect of different choices for the branch predictor using sim-outorder function in Simple scalar, which
models all the execution aspects of an Alpha 21264 processor. The CPI and Hit rates were used as parameters for
comparison of different branch predictors.
Advanced Digital Logic Projects (Sep’15-Dec’15)
 Implemented 4x4 bit serial multiplier using design vision. Simulated FSM based pump control scheme for Mealy and
Moore machines; Analyzed stuck at faults and performed automatic test generation pattern (ATPG) for various logic
circuits using Tetramax. Formulated Integer Linear Programming(ILP) for graph sequencing using CPLEX tool.
Smart Pharmacist using drone technology (Feb’16-May’16)
 Designed drones to make medicines more accessible for people who have limited mobility by dropping the medicines
to a person’s doorstep. Conical horn antenna is used for radars signals to drop the package and Helical antenna is
used to communicate with the base station – pharmacy in this case.
SENIOR DESIGN PROJECT AND INTERNSHIP
QOE Based Dynamic Resource Allocation for Unperceivable Video Fluctuation in LTE
Mentored by Ericsson India Global Services. - Efficient allocation of network resources for video delivery in LTE is done using
Quality of Experience (QOE) that allocates resources dynamically enhancing the quality of video streaming for multiple users.
RESEARCH AND PUBLICATION
 Automated System for monitoring and Detection of Driver’s Fatigue in 6th International Conference on Advanced
Computing and Communication Technologies (ICACCT). (Dec’12)
HONOURS AND ACTIVITIES
 Long Term Evolution (LTE) experts selected my team research idea in one among the top nine in an International
competition held at New York during my internship at Ericsson Global Services Private Limited.