The document lists 8 experiments for an Advanced Digital System Design lab practical examination for students in the Embedded System Technologies branch of EEE at SRI SHAKTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY. The experiments involve designing basic digital circuits like adders, multipliers, ALUs, and shift registers using VHDL and Verilog, simulating the designs using Xilinx or Altera software, and implementing the designs on Xilinx or Altera FPGAs.

1. SRI SHAKTHI
INSTITUTE OF ENGINEERING AND TECHNOLOGY
COIMBATORE – 641 062
(An Autonomous Institution, Affiliated to Anna University)
PRACTICAL EXAMINATION NOV / DEC-2019
Branch Name: EEE ME-Embedded System Technologies
Date & Session of Exam: 28.01.2020 & FN
Course Code/Name: P19EMTL102L / ADVANCED DIGITAL SYSTEM DESIGN LAB
Semester/ Year: I/I
LIST OF EXPERIMENTS
1 Design an Adder (Min 8 Bit) using VHDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
2 Design a Multiplier (4 Bit Min) using VHDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
3 Design an ALU using VHDL. Simulate it using Xilinx/Altera Software and implement
by Xilinx/Altera FPGA
4 Design a Universal Shift Register using VHDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
5 Design an Adder (Min 8 Bit) using Verilog. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
6 Design a Multiplier (4 Bit Min) using Verilog. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
7 Design a Universal Shift Register using Verilog. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
8 Design an ALU using Verilog. Simulate it using Xilinx/Altera Software and implement
by Xilinx/Altera FPGA
InternalExaminer ExternalExaminer