The document summarizes a thesis presentation on verifying configurable Networks-on-Chip (NoCs) using a Universal Verification Methodology (UVM)-based tool. The presentation outlines the research goals of proposing a UVM verification architecture to verify NoCs with different topologies, routing algorithms, and flow control. It describes case studies on a base router and configurable Daniel router. It proposes generic UVM architectures and error injection methodologies to support simulation and hardware emulation of NoCs. Simulation results on performance metrics and functional coverage techniques are also summarized.

1. Thesis Defence,17th of February, 2019, Cairo © 2019Thesis Defence,17th of February, 2019, Cairo © 2019
On the Verification of Configurable NoCs
in Simulation and Hardware Emulation: A
UVM-based Tool
Presented by: Sameh Mahmoud El-Ashry
Master of Science in Computer and Systems Engineering, Ain Shams University, Cairo, Egypt
Supervised By
Prof. Dr. Mohamed Watheq Ali Kamel El-Kharashi
Dr. Ahmed Mohammed Mohammed Hamada Shalaby
Dr. Mohamed AbdelSalam Ahmed Hassan

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Outlines
◎ Research Goals and Tool Design Flow.
◎ Introduction.
○ Why NoC?
○ Motivation
○ Why UVM for NoC Error-Injection?
◎ Case Studies.
○ A Base Router
○ Configurable Router: Daniel Router
◎ Proposed UVM Architectures to Support Simulation and Hardware Emulation.
◎ Proposed UVM Error Injection Methodologies.
◎ Simulation Results and NoC Performance Metrics.
◎ Proposed Functional Coverage Technique.
◎ Conclusion & Future Work.
◎ Publications.
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Research Goals
❑ This research aims is to propose configurable verification tool-based user
scripts based UVM methodology, which are implemented by the author.
❑ Extracting the verification requirements and proposing a novel UVM
verification architecture.
❑ By proposing UVM architecture to verify the 2D/3D NOCs with different
network topologies, routing algorithms and flow control methodologies.
❑ The architecture supports simulation and hardware emulation platforms.
❑ Simulate/Emulate the configurable verification tool with a Network on Chip
Designs.
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Tool Design Flow
4
NoC Generation Simulation or Hardware
Emulation
Error-Injection Optional Phase Performance Evaluation
NoC Verification Environment
Generation
Simulation or Hardware
Emulation
Error-Injection Optional Phase Automated Checking End-to-
End
NoC
library
Perl
Scripts
R1
NI
R2
NI
R3
NI
R4
NI
R5
NI
R6
NI
R7
NI
R8
NI
R9
NI
Interface
Configurable UVM
Environment

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Why NOC? Network on Chip (NoC) Vs Bus
NoC has become the trend for Multicore systems’ interconnections
BUS
IP
1
IP
2
IP
3
IP
4
IP
5
IP
6
IP
7
IP
8
IP
9
IP
10
IP
11
IP
12
IP
13
IP
14
IP
15
IP
16
IP
9
IP
10
R1
IP1
NI
R2
IP2
NI
R3
IP3
NI
R4
IP4
NI
R5
IP5
NI
R6
IP6
NI
R7
IP7
NI
R8
IP8
NI
R9
IP9
NI
R10
IP10
NI
R11
IP11
NI
R12
IP12
NI
R13
IP13
NI
R14
IP14
NI
R15
IP15
NI
R16
IP16
NI
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Noc-based Communications
◎NoC is a feasible and promising alternative solution to the problems
adopted by bus-based systems.
◎It’s the most viable solution to cope with scalability of many-core systems as
it meets performance, power and reliability requirements.
◎Controlling several NoC parameters such as Topology, Routing Algorithm
and Flow Control greatly affect NoC performance.
◎Topology is chosen to match the optimal architecture.
◎Routing Algorithm achieves load balancing and low latency.
◎Flow Control determines how resources are shared among packets and how
fairness is accomplished.
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Motiviation
Digital Systems
performance depends on
interconnections
NoC to improve
performance
Seeking reliability
and scalability of
NoC
Importance of Testbench
Verification architecture
UVM
UVM features for
NOC reusability
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Why UVM (Universal Verification Methodology) for NoC Error-Injection?
We want to check
that NoC systems
meet design
specifications.
We build verification
environments to validate the
reliability of NoC different
architectures.
We inject errors to
verify that the system
either handles them or
ignores them.
We cannot use traditional
testbenches because NoCs
are complex and scalable
systems.
We use UVM as it
contains generic
components that
can be reused.
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Role of the UVM Environment
◎The proposed UVM environments to mimic processor elements
connected to NoC routers at some ports.
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Dependences between faults, errors, and failures
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Thesis Contributions
◎Designing generic, scalable, and reusable UVM architecture for NoCs using
simulation and hardware emulation environments.
◎Applying different error-injection approaches for NoCs through the proposed
generic UVM environments.
◎Mapping of NoC parameters to UVM layers to achieve the re-usability while
changing router type.
◎Evaluating the base router and Daniel router as different case studies using the
generic UVM architecture.
◎Applying functional coverage techniques to catch the source of injected errors.
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Comparison between the proposed verification framework and
open source tools
12
Connect MAIA ATLAS Proposed
verification
framework
Tool type RTL
generator
RTL
generator
RTL
generator
Verification
environment
generator
Testbench
framework
Ad-hoc
Verilog
Ad-hoc
Verilog
Ad-hoc
SystemC
UVM
based
Error
injection
mechanism
Not
Supported
Not
Supported
Not
Supported
Supported
Simulation
platform
Supported Supported Supported Supported
Emulation
platform
Not
Supported
Not
Supported
Not
Supported
Supported
Verification
environment
Topology
dependent
Topology
dependent
Topology
dependent
Topology
independent

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Case Studies
A Base Router A Configurable
Router: Daniel Router
Input port
East
West
North
South
Local
Output port
East
West
North
South
Local
ReqCntReqUpstr
GntUpstr
FullUpstr
PacketIn
ReqDnstr
GntDnstr
FullDnstr
PacketOut
GntCnt
Packet
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The routers parameters and configurations
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Parameters Configurations
Topology Mesh, torus and butterfly.
Flow control Store and Forward.
VCs Variable number of VCs per port.
Buffers size Variable number for total input buffer size per port in flits.
Buffer management Static buffer management.
Flit size Variable number of bits for each flit.
Routing algorithm Deterministic.
Arbiter Round robin arbiter.
Maximum payload length Variable number of body flits per packet.
VC allocation type Separable input-first, separable output-first, and wave
front based VC allocation.
Traffic patterns Hot spot, bit-reversal , and uniform.

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Proposed Generic UVM
Architectures for NoC Platforms
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Traditional
Universal Verification Methodology (UVM)
❑ UVM:
- A complete verification environment composed of reusable verification
components.
- Needs no re-construction when design under test (DUT) changes.
- A comprehensive methodology of constrained-random, coverage-driven
verification.
* Basic UVM, Verification Academy.
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UVM for Router Vs UVM for NoC
❑
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Proposed UVM Error Injection Methodologies for NoC Platforms
◎Faulty UVM sequence item or
transaction.
◎Faulty UVM reference model.
◎Bus error-injector agent
between routers.
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Proposed UVM Architecture to Support Error
Injection Techniques
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Proposed Generic UVM Architecture for NoC
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A Detailed Description of Scoreboard Organization
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Proposed Generic UVM Environment for NoC
Emulation Platforms
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Novel dynamic error injection methodolgy using
hardware emulation for NoC platforms
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Mapping NoC parameters to UVM layers
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Simulation Results and NoC Performance Metrics1
◎Figs show the throughput and latency results respectively for 64-ary mesh and torus topologies for the
base router using 64-bit buffer size with a uniform distribution traffic pattern.
◎Results clearly show that the mesh topology has lower throughput and higher latency, as expected.
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Throughput results of different network sizes for base router. Throughput results of different network sizes for base router.

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Simulation Results and NoC Performance Metrics2
◎we find that increasing the number of nodes per network will subsequently decrease the average
throughput and increase the average latency.
◎We also found that Torus topology has the highest average throughput and the lowest average
latency.
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Throughput results of different network sizes for daniel router. Latency results of different network sizes for daniel router.

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Simulation Results and NoC Performance Metrics3
◎Experiments have been done using the 8x8 mesh topology network through a different
number of VCs; 1, 2 and 3.
◎Increasing number of VCs improves the network performance.
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Throughput results of different number of VCs for Daniel router. Latency results of different number of VCs for daniel router.

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Simulation Results and NoC Performance Metrics4
◎Buffer size is the number of flits that can be held by the buffer.
◎Increasing buffer size improves the throughput, which improves the network performance at the
expense of the network area and power.
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Throughput results of different buffer sizes for daniel router. Latency results of different buffer sizes for daniel router.

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Simulation Results: Case Studies Response (Error-Injection)
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NoC miss-routing detection using functional coverage
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Functional coverage evaluation results between
pure and faulty RTL.
❑ Functional coverage results are evaluated according to the comparison between pure and
faulty RTL based on the implementation of one hundred coverpoints.
❑Coverage results are obtained by injecting functional errors through negative test
scenarios.
❑Results show that the functional coverage percentage is decreasing in a nonlinear relation
with respect to the cascaded errors that may happen due to the injected errors.
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Number of injected
errors per one test
scenario
Percentage for pure
RTL
Percentage for faulty
RTL
2 100% 98%
4 100% 92%
7 100% 80%

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Conclusions
❑ This thesis presented reusable mechanisms for NoC platforms using UVM.
❑ A novel methodology of error injection based on bus-injector is proposed to detect NoC
transmission errors in the simulation environment.
❑ Verification plan for negative scenarios are applied to two NoC case studies and results
are evaluated to detect and check the error severity in the UVM SB.
❑ Experimental results show the efficiency of proposed techniques when adopting them
using UVM.
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Future Work
❑ Our future work would integrate the proposed UVM simulation environment to our
previous work [6] with RISC-V cores in NoC. The UVM environment will drive few
local ports, as shown in Figure and the other ports are driven by RISC-V processors.
❑ The aim of the future work is to ensure that all variants of our RISC-V processors may
handle error scenarios correctly and can respond to any type of error from the surrounding
components without crashing or freezing.
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Formal Publications of the Thesis
[1] S. El-Ashry, H. Ibrahim, M. A. Ibrahem, M. Khamis, A. Shalaby, M. AbdElsalam, and M. W. El-Kharashi. “On error injection for
NoC platforms: A UVM-based practical case study”. In Proceedings of the 10th International Workshop on Network on Chip
Architectures (NoCArc 2017), held in conjunction with the 50th Annual IEEE/ACM International Symposium on Microarcchitectures
(MICRO-50), article no. 2, Cambridge, MA, USA, October 15, 2017.
[2] Khamis, M., El-Ashry, S., Shalaby, A., AbdElsalam, M., & El-Kharashi, M. W. (2018, October). A Configurable RISC-V for
NoC-Based MPSoCs: A Framework for Hardware Emulation. In 2018 11th International Workshop on Network on Chip
Architectures (NoCArc) (pp. 1-6). IEEE.
[3] S. El-Ashry, M. Khamis, H. Ibrahim, A. Shalaby, M. AbdElsalam, and M. W. El-Kharashi. “On Error Injection for NoC
Platforms: A UVM-based Generic Verification Environment”. Submitted to IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems.
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Previous NoC Publications from Graduation Projects
[4] A. El-Naggar, E. Massoud, A. Medhat, H. Ibrahim, B. Al-Abassy, S. El-Ashry, M. Khamis, and A.
Shalaby,“A Narrative of UVM testbench environment for interconnection routers: A practical approach”, in
Proceedings of the 11th International Design & Test Symposium (IDT), 2016, pp. 98-103.
[5] A. S. Eissa, M. A. Ibrahem, M. A. Elmohr, Y. Zamzam, A. El-Yamany, S. El-Ashry, M. Khamis, and
A. Shalaby, “A reusable verification environment for NoC Platforms using UVM” in Proceedings of 17th
IEEE International Conference on Smart Technologies (EUROCON), 2017.
[6] Elmohr, M.A., Eissa, A.S., Ibrahim, M., Khamis, M., El-Ashry, S., Shalaby, A., AbdElsalam, M. and
El-Kharashi, M.W., 2018, March. RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC. In
Parallel, Distributed and Network-based Processing (PDP), 2018 26th Euromicro International Conference
on (pp. 617-621). IEEE.
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Acknowledge
◎ I want to thank all the attendees who come to support me.
◎ I want to express my thanks and gratitude to my advisors, Prof. Dr. Mohamed Watheq El-Kharashi,
Dr. Ahmed Shalaby, and Dr. Mohamed AbdelSalam for their support, encouragement and their efforts
and guidance to achieve strong contribution.
◎ I want to thank my colleague Mostafa Khamis for his collaboration with me and be responsible for
the design side to help me applying my verification ideas on his design.
◎ I wish to thank my wife Shahd Elkabbary for her support towards the defense during the
preparation for our wedding.
◎ Finally, I want to thank my parents, sister and friends, their supportive words and encouraging
messages kept me motivated to work harder and be a better engineer in the academia and the
industry.
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Thanks for your attention
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38. Thesis Defence,17th of February, 2019, Cairo © 2019
Questions?